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UNIVERSITY OF ILLINOIS
GRADUATE COLLEGE
DIGITAL COMPUTER LABORATORY
T
REPORT NO. 160
THE ARITHMETIC SUBSYSTEM
OF THE
NEW ILLINOIS COMPUTER
by
J. 0. Penhollow
January 2k, I96U
This work was supported in part by the
Atomic Energy Commission under Contract No„ AT(lll)Ul5
Return this book on or before the
Latest Date stamped below.
Theft, mutilation, and underlining of books
are reasons for disciplinary action and may
result in dismissal from the University.
University of Illinois Library
25
NOV 2 9 '^
NOV 1 1 R
PCD
L161— O1096
UNIVERSITY OF ILLINOIS
GRADUATE COLLEGE
DIGITAL COMPUTER LABORATORY
REPORT NO, 160
THE ARITHMETIC SUBSYSTEM
OF THE
NEW ILLINOIS COMPUTER
by
J. 0. Penhollow
January 2k, 196k
This work was supported in part by the
Atomic Energy Commission under Contract No„ AT(lll)4l5
fk . J
ACKNOWLEDGMENTS
The design and development of the Arithmetic Subsystem of the new Ill
inois computer was accomplished through the efforts of many people. To name
all of them would be difficult, "but a few deserve special recognition.
D. E. Muller, J. E. Robertson, D. B. Gillies, D. J. Wheeler, W. J. Poppel
baum, and G. Metze contributed many of the basic concepts which are incorporated
in the present design.
The original set of logic circuits was developed by W. J. Poppelbaum
and N. E. Wiseman. These circuits were later modified and augmented by J, E. Rob
ertson, G. Metze, K. C. Smith, and H, Guckel,
H. Aiso, M. Faiman, R. R. Shively, R. E. Swartwout, and the author
completed the final logic design under the competent and energetic leadership
of D. B. Gillies. The work of this group was also directed and influenced by the
advice and criticism of R. E. Meagher, J. E. Robertson, and D. E. Muller, A
number of errors in the final design of delayed control were discovered and cor
rected by R. H. Farrell.
In the development stage, the design group benefited from the counsel
and guidance of J. E„ Robertson, C. E. Carter, H„ E. Lopeman, and T. E, Kerker
ing. The set of logic drawings which describe the subsystem was produced by
H, Aiso, R. E. Swartwout and the author with the help of H. E. Lopeman, So P.
Krabbe, R. F. Kingsley, K. C. Law, J. K. Burr ell, and other members of the draft
ing department. The component layout was accomplished by R. L. Cummings, M, D.
Freedman, R. F. Kingsley, S. P. Krabbe, and L. J. Peck under the direction of
H. E, Lopeman and A. F. Irwin, T. E, Kerkering and F. P. Serio supervised the
construction.
•111
TABLE OF CONTENTS
P( g<
1. INTRODUCTION 1
2. ORGANIZATION OF THE ARITHMETIC SUBSYSTEM AND ITS RELATIONSHIP
WITH THE EXECUTIVE SUBSYSTEM 6
3. THE ARITHMETIC UNIT 10
3.1 The Main Arithmetic Unit 10
3.1.1 A Summary of the MAU Logic l6
3.1.2 The MAU Bit Path Logic 21
3.1.2.1 The Fl to M Path 22
3.1.2.2 The R to M Path 22
3.1.2.3 The M Register 22
3.1.2.4 The MsA Selector 23
3.1.2.5 The MsS Selector. 24
3.1.2.6 The sA Selector 24
3.1.2.7 The A Register 30
3.1.2.8 The sS Selector 31
3.1.2.9 The S Register 37
3.1.2.10 The sQ Selector
3.1.2.11 The Q Register 39
3.1.2.12 The sR Selector 40
3.1.2.13 The R Register 42
3.1.2.14 The R to FO Path 42
3.1.3 Standard Base 4 Pseudo Adders 45
3.1.4 High Special Adders 48
3.1.5 Low Special Adders 52
3.1.6 One Digit Assimilators 57
3.1.7 Zero Detectors and RoundOff Logic 58
3.1.8 Carry Generator , 60
3.1.9 The a Logic 65
3.1.10 The A, S, M and R Normalization Logic 67
3.1.11 Sign A and Sign Comparison Logic 69
3.1.12 The Q and R Half Subtracters 70
3.1.13 The CarryBorrow Logic 74
3.1.14 The Q Decoder 78
3.1.15 The u Decoder 79
3.1.16 The Division Predictors (p Decoders) 87
3.1.17 The Quotient "Bit" Recoder and the BorrowSubtractor . . 106
3.2 The Exponent Arithmetic Unit Il6
3.2.1 A Summary of the EAU Logic 120
3.2.2 The EAU Bit Path Logic 120
3.2.2.1 The Fl to EM Path 120
3.2.2.2 The EM Register and the EM = 64 Logic 121
3.2.2.3 The sD Selector 121
3.2.2.4 The sEA Selector , 123
3.2.2.5 The EA Register 123
3.2.2.6 The ES Register and the ES to F0 Path 124
3.2.2.7 The sE Selector 124
3.2.2.8 The E Register 125
IV
TABLE OF CONTENTS (CONTINUED)
Page
3.2.3 The Exponent Adder (DAdder) 126
3.2.U The Exponent Decoder 128
THE LINK MECHANISMS 135
k,l Gates 137
h.2 Selector Mechanisms lUo
U.3 Control Status Memory Elements l^t8
DELAYED CONTROL 15U
5.1 The Decode Sequence G l6l
5.2 The Clear Add Sequence G Yjh
5.3 The Correct Overflow and Detect Zero Sequence K 179
5.U The Load Q Sequence L 183
5.5 The Add Sequence A 185
5.6 The Exponent Arithmetic Sequence E . . . . 20k
5.7 The Store Sequence S 205
5.8 The Shift Sequence F 212
5.9 The Store Preliminaries Sequence P 217
5.10 The Normalize Sequence R 219
5.11 The Difference Absolute Value Sequence V 221
5.12 The Multiply Sequence M 222
5.13 The Division Sequence D 226
v
1 . INTRODUCTION
The new Illinois computer is composed of four major subsystems as shown
in Fig. I. The Executive Subsystem includes Advanced Control (AC) with its count
ers and interlocks, the Address Arithmetic Unit (AAU), and the Flow Gating Memory
(FG). The Arithmetic Subsystem contains Delayed Control (DC), the Link Mechanisms
(LM), and the Arithmetic Unit (AU). The Core Memory Subsystem presently contains
a U096 word Core Memory (c) with its control, selection, and buffering logic. The
Interplay Subsystem includes auxiliary storage, i/O devices, and the associated
control logic.
This report presents a comprehensive description of the logical struc
ture and function of the Arithmetic Subsystem. It is written primarily as a
reference for those with maintenance responsibilities. As such, it does not dwell
on the underlying philosophy.
The reader is assumed to be familiar with the Delayed Control order
code as defined in File No. U58, "Order Code for the New Illinois Computer," by
D. B. Gillies. It is recommended that the reader obtain the set of drawings en
titled "Logic Drawings for the Arithmetic Subsystem." In the discussion of the
subsystem logic, frequent reference is made to this set of drawings, and in par
ticular to the drawing (D1128) entitled "Composite Flow Chart for all MAU and
FAU Arithmetic Operations." Throughout the report, the drawings included in this
set are referred to by number; e.g., D1128. The following reports are recom
mended as references: File No. 319 > "Theory of Computer Arithmetic Employed in
the Design of the New Computer at the University of Illinois," by J. E. Robertson:
File No. 397, "A Description of the Operation of Delayed Control in Terms of Its
Flow Charts," by D. B Gillies; File No. 388, "One Method for Designing SpeedIn
[dependent Logic for a Control," by R. E. Swartwout; and File No. 528, "A Descrip
tion of the Logic Drawings for the Arithmetic Subsystem," by J. 0. Penhollow.
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The nomenclature used in this report agrees with that shown on the
"Logic Drawings for the Arithmetic Subsystem, " except that suffixes on signal
names are usually omitted if their purpose is to distinguish signals which are
logically identical hut electronically different. In line with this policy, no
special attempt is made to explain the existence of logical identity elements
such as emitter followers and noninverting amplifiers or cable drivers.
Throughout the report, "1" and "0" denote positive and negative volt
age levels respectively. If a memory element such as Z is set to "1," its true
or "1" side output  designated z  has a logic value of "1," meaning the z
signal voltage is positive with respect to ground. In this state, the false or
"0" side output  designated z  has a logic value of "0" meaning the z sig
nal voltage is negative with respect to ground. If Z is set to "0," z and z
have logic values of "0" and "1" respectively. The parity of the signal used to
set a memory element to a particular state depends on the type of memory element
under consideration. It is worthwhile to note that memory elements and their
inputs are generally designated by capital letters, while their outputs are des
ignated by the same letters in lower case. On this and other questions of nomen
clature, the reader is referred to File Wo. 528 as indicated above.
The symbolism used to denote the thirteen basic control sequences which
form Delayed Control is defined at the beginning of section 5 of this report.
For example, A denotes the floating add sequence, and S denotes the store se
quence. This notation agrees with that shown on the "Composite Flow Chart for
all MAU and EAU Operations" (D1128).
A word of caution is in order concerning the Boolean expressions which
define conditional branching on the composite flow chart . Control takes a par
ticular branch if the corresponding Boolean expression has a logic value of "1"
or equivalently if its dual has a logic value of "0." The Boolean expressions
which appear on the composite flow chart are considered positive logic and their
duals negative logic. Due to the nature of the control circuitry, the "branch
conditions are realized with negative logic in the machine, and they appear in
this form on the control logic drawings.
The report begins with a general description of the organization of the
Arithmetic Subsystem and its relationship to the Executive Subsystem in section
2. No attempt is made to evaluate the merits of this relationship.
Section 3 contains a lengthy discussion of the Arithmetic Unit which
includes the Main Arithmetic Unit (MAU), the Exponent Arithmetic Unit (EAU),
and all encoders or decoders which either feed or are fed by the registers,
selectors, and adders of the MAU and EAUo The Boolean expressions for each un
it of logic in the MAU and EAU are defined and discussed. The purpose and func
tion of each unit is indicated with reference to the DC order code. In certain
cases the logic is analyzed to provide additional insight.
It should be kept in mind that section 3 treats each unit of logic in
the Arithmetic Unit as a separate entity. A particular unit may be used during
the execution of many different DC orders; however, the purpose it serves may
not be the same in all cases. In an attempt to illustrate this fact, the pur
pose of each unit is described relative to all of the DC orders which use it.
This description generally does not include the operational details of the cor
responding control sequences. However, the halfsubtractors, multiplier recod
ers, and division predictors are so specialized that their description includes
some of these details for reasons of clarity.
The Link Mechanisms (LM) are discussed in section k. These include
gates, selector mechanisms, and status memory elements. Delayed Control governs
the data flow in the Arithmetic Unit via these devices. The operation of each
type of Link Mechanism is described in this context.
Section 5 describes Delayed Control in terms of its thirteen basic se
quences. The discussion is supplemented with pertinent references to those
k
sections which describe the Arithmetic Unit and the Link Mechanisms., A descrip
tion of the signal flow through the decode G _, clear add B , and correct over
flow K sequences is presented to illustrate the characteristics of speed
independent control logic. The reader is referred to File Ko. 388 by R. E. Swart
wout for a more thorough treatment of this topic o
5
2. ORGANIZATION OF THE ARITHMETIC SUBSYSTEM AND ITS RELATIONSHIP
WITH THE EXECUTIVE SUBSYSTEM
A block diagram of the Arithmetic Subsystem is shown on the right half
of Fig. 2. The subsystem is capable of performing base k floating point arith
metic and a limited set of logical operations as described in File No. k^Q by
D. B. Gillies. The input and output operand channels carry 52 bits in parallel.
The first U5 bits of the operand are generally interpreted as a fraction in the
range: 1 < f < 1. The last 7 bits are generally interpreted as an integer
base k exponent in the range: 6k < x < 6k. Both the fraction and the exponent
have a complement representation. The other data channel between the Executive
and Arithmetic Subsystems carries a 6 bit Delayed Control (DC) order which spec
ifies the operation performed by the Arithmetic Subsystem.
As shown in Fig. 2, the Arithmetic Subsystem is composed of three prin
cipal units. The Arithmetic Unit (AU) contains the computational logic and is
divided into two major subunits as indicated. The Main Arithmetic Unit (MAU)
and the Exponent Arithmetic Unit (EAU) handle the fractional and exponential
calculations respectively. The second principal unit of the subsystem contains
the Link Mechanism (LM) logic. This logic transmits commands from the Delayed
Control (DC) to the Arithmetic Unit (AU). It may be further subdivided into
gate and selector mechanisms and status memory elements. Delayed Control (DC)
is the third principal unit of the Arithmetic Subsystem. The DC logic governs
the data flow in the AU via the LM.
A block diagram of the Executive Subsystem is shown on the left half
of Fig. 2. This subsystem supervises the execution of the stored program. The
other three subsystems are subordinate in the sense that they receive their ord
ers from the Executive Subsystem. The Executive Subsystem transfers command words
of the stored program from Core to the Flow Gating Memory, where it sequentially
examines the individual orders. It executes an order or portions of an order
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for which it has the capability. Otherwise, it assigns all or part of the order
to an appropriate subsystem. In the latter case, the Executive Subsystem may
send and/or receive a corresponding operand. Address modification, indexing,
and certain control transfer orders are executed within the Executive Subsystem.
All orders requiring the transfer of operands between Flow Gating Memory and
Core are partially or totally executed by the Executive Subsystem.
To provide a background for the detailed description of the Arith
metic Subsystem, we briefly consider the functional relationship between it
and the Executive Subsystem. The reader is referred to File No. k6k, "Advanced
Control," by R. R. Shively for a comprehensive discussion of the purpose and
function of the Executive Subsystem and its relationship with the Arithmetic
Subsystem.
When Advanced Control (AC) of the Executive Subsystem encounters an
order which must be assigned to Delayed Control (DC) of the Arithmetic Subsys
tem, it first decides whether the order presently held in the Delayed Control
Order Register (DCR) has been decoded and initiated by DC. If so, AC transfers
the new order to DCR. If not, AC may have to wait until DC completes its pres
ent order and decodes the order in DCR. If the order requires an initial op
erand, AC determines whether DC has used the operand presently held in the IN
register (i.e., the Fl register of the Flow Gating Memory). If so, AC places
the new operand in IN; otherwise, it must wait unless there are other orders
which it may perform or assign. If the order requires a terminal operand
(i.e., a DC store order), AC checks the contents of the OUT register (i.e., the
FO register of the Flow Gating Memory) and its Core address in the WA register.
As long as no initial operand is required, DC is permitted to initiate the store
order even though the Executive Subsystem has not transferred the present con
tents of OUT to the Core address held by WA. However, DC cannot complete the
store order until this transfer is made. As soon as Out Write Control (a part
8
of the Executive Subsystem) has transferred the present contents of OUT to Core,
AC places the new Core address in WA. DC is then free to gate the terminal op
erand from the AU into OUT and thus complete its part of the store order.
There are four special DC store orders which have initial and termi
nal operands with the same Core address. These are ASC, SSC, XCH, and SEQ.
When AC encounters one of these orders, it must check and load DCR and IN under
the conditions given above. If the present contents of OUT have been stored
in Core, the new Core address is placed in WA and DC is permitted to gate the
terminal operand into OUT.
In summary, the Executive and Arithmetic Subsystems operate concurrent
ly but not in a completely independent manner. The former assigns orders and op
erands to the latter and accepts operands as a result. The Executive Subsystem
has no control over the time or equipment used by the Arithmetic Subsystem to
obtain a result. With few exceptions, the Executive Subsystem is capable of
assigning a new order to the Arithmetic Subsystem before the latter has com
pleted its current order. As implied above, there are circumstances in which the
Arithmetic Subsystem is forced to wait on the Executive Subsystem. However, these
circumstances can either be avoided or minimized by careful programming.
3. THE ARITHMETIC UNIT
The Arithmetic Unit (AU) consists of the Main Arithmetic Unit (MAU)
and the Exponent Arithmetic Unit (EAU). These two units operate concurrently,
but are physically and logically distinct. Both receive their operands from
the 52 bit IN register. The first 4 5 bits of this are usually interpreted as
a fraction, 1 < f < 1, and is the MAU operand. The last 7 bits are usually
interpreted as an exponent, 6k < x < 6h , and is the EAU operand. The com
plete floating point operand contained by IN may be expressed as p = f • k .
Floating point results placed in OUT have the same form. Both f and x are in
complement representation. In the case of logical orders other than SRS and LRS,
x is not used by the EAU, and the MAU interpret s f as a U5 bit word without
sign. The same is true for the orders SRS and LRS except that x is used by the
EAU to govern the number of base h shifts. In strictly exponent operations the
MAU is not active and thus does not use f . Neither f nor x are used during the
execution of store orders which do not require an initial operand.
3.1 The Main Arithmetic Unit
The general topology of the MAU is shown in Fig. 3« Registers A, M,
Q and R each have U6 bits, while S has k& bits. Since the two adders yield
sums in base k stored carry representation, A and S also contain 23 and 2h
stored carry bits respectively. Three stored carry bits are also associated with
the Q and R registers to facilitate the performance of certain additions, mul
tiplication, and division. With regard to these special bits, the term "stored
carry" is inaccurate, since some of them have negative weight. The bits asso
ciated with each of the five registers are indicated below. Stored carry bits
are designated with an asterisk.
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8. 3 S  2 S i S o S l S 2 S l1 S i S U 3 S UU
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The MAU does modulo h arithmetic. The weight of a bit in the i — po
sition (stored carry or otherwise) is 2 . The point is assumed to lie "between
the — and 1 — hit position, so the largest range of f that can be associated
with every register of the MAU is 2 < f < 2. If the bits S , S and S are
ignored, the positive limit on f in the A and S registers is less than 8/3.
The limit, 8/3, is obtained by assuming an infinite stored carry representa
tion.
The function of each register in the MAU is briefly described below.
During the decode step (Gl) of every DC order, the gate FlgMEM transfers the
12
first hj bits of IN to M even though the order does not use an initial operand.
The IN hit is mapped into M and M . The results of the previous DC opera
tion are generally held in A and Q which represent the primary rank of the dou
ble length accumulator. The S and R registers form the secondary rank of the
double length accumulator which usually holds an intermediate result at the end
of a DC operation. An exception occurs in the case of divide orders. At the
end of any divide order , A contains the fractional quotient, Q, contains zeros,
and R contains the fractional remainder. During the store step (S9) of every
DC store order, the RESgPO gate transfers a modified copy of R to the OUT register,
The nature of the modification depends on the store order and will be discussed
in detail later. It is immediately clear, however, that a bit for bit transfer
is impossible since the information contained in k6 bits of R must be stored in
the first U5 bits of OUT.
The two adders shown in Fig. 3 are composed of base h pseudo adder
modules which are standard except at the most and least significant ends of the
A and S registers. The A adder has the contents of the A register as one input
and the output of the MsA selector as the other. In either case, the selector
output in two's complement representation is added to the stored carry repres
entation held in A or S. A subtraction is accomplished by causing M to appear
th
at the selector output and then adding an extra bit, ca or cs, in the kk — po
sition. The outputs of the A and S adders are designated as C£ and a respec
tively, and are generally in stored carry representation. Let a, s, and m re
present the contents of A, S, and M. The values of Ot and in terms of a, s,
and m under various M selector settings are given below. Since the M selector
mechanisms have memory, the choice of a particular setting remains in effect
until a new choice is made.
■13
2 MsA: a = a + 2m
MsA: a = a + m
OMsA: a = a +
MsA: a = a  m
KgA: a = a + k
The representation of a and cc may not "be the
same since the adder propagates the stored
carries of "a" over one "base k position „
In this notation, k denotes the output of the
carry generator., As a result, QL is the as
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similated form of a: i.e., QL. = for all i.
i
2MsS:
= s + 2m
MsS;
= s + m
.S:
= s +
CS:
= s + 2
MMsS:
= s  2
KMsS:
= s +
The comment concerning a = a + also applies
here. As a consequence of the nature of the
MsS selector mechanism, the OMsS setting can
only be used following a setting of 2MsS, MsS,
MsS. Otherwise KMsS must be used.
kk
kk
This setting is used following a setting of
CS or MMsS.
The fact that stored carries are permitted in A and S but not else
where, implies they must be assimilated whenever transfer to another register
is necessary. The purpose of the carry generator logic is to permit the as
similation of all stored carries in A by one pass through the A adder. The
carry generator was first proposed and described by D. J. Wheeler in Report
No. 92 entitled "The Arithmetic Unit." In effect, it generates a carry word
which may have "l's" in the even bit positions and always has "O's" in the
odd bit positions. An even bit position will contain a "l" if the assimila
tion of all base k stored carries in A will cause a carry into that position.
Ik
The addition of this carry word to the contents of A yields an assimilated re
presentation of A, provided the generated stored carries are suppressed.
The sAQ and sSR selector mechanisms also have memory. Once a par
ticular selector setting has been chosen by DC, it remains in effect until
a new setting is made. The settings shown in Fig. 3 are easily interpreted,
provided the outputs of the A and S adders are used in place of the register
outputs. The effect of these settings is indicated below. The presence of
&&> gQj gS and gR above the arrows implies that these gates must be active
before the selector outputs can be transferred to the associated registers.
1/1+ AQsSR: l/k a S S S, l/k Q g  R
OAsSR: Q S 5s, a g S R
k AQsSR: k a g S S, k Q g 5. R
gS gR
OAsSR: 6 + S, a &* R
OsSR: g 5s, €r
1/1+ SRsAQ: l/k a S  A, l/k R g S Q
SRsAQ: a S ^ A, R g S Q
k SRsAQ: 1+ a ^ A, k R g S
Q
SOsAQ: a g ^ A, g S Q
Since Q and R represent extensions of the A and S registers respec
tively, l/k AQsSR and gR causes a, , CCi. , and CC, , to be mapped into R , R ,
and R . Likewise, k SRsAQ and gA causes r (p ) and r (p ) to be mapped
into A. and A, , . Similar interpretations must be made for the other options,
A detailed discussion of the logical connections at the ends of the A, S, Q and
R registers is given in section 3«1«2.
The gate mechanisms do not have memory, so DC must activate them each
time the contents of the associated registers are changed. If the gate is not
activated, the register simply retains its old contents regardless of the bit
15
configuration appearing at its inputs. The two special gates which have not
been mentioned so far are R • MgM and R ^ MgM. Their notation suggests their
action. R • MgM transfers the zeros of R into M. The "bitwise AND of the pre
vious contents of M and the contents of R is left in M. Likewise, R v MgM
transfers the ones of R into M, yielding the "bitwise OR of M and R. When
R " MgM and R ^ MgM are active together, the contents of R are simply trans
ferred to M.
3.1.1 A Summary of the MAU Logic
The logic associated with the MAU is completely illustrated in a
series of 15 drawings. These drawings are part of the set of drawings enti
tled "Logic Drawings for the Arithmetic Subsystem." A summary of the logic
shown on each of these drawings follows .
"Standard A, S and M Logic" (SAS) D170T illustrates a standard
U bit cross section of the A, S and M registers with their associated gates
and selectors. The standard base h pseudo adders are shown in block form.
This logic is physically located on the Q, A and S chassis of a standard
MAU bay, e.g. 3F or 3R.
"High A, S and M Logic" (HAS) D1522 describes the logic at the
most significant ends of the A, S and M registers down to and including bits
A, , Si, and M, . Gates, selectors, and some of the high A and S end connection
logic appear in detail on this drawing. The standard base k pseudo adders,
and the high A and S special adders are shown in block form. The logic shown
on this drawing is physically located on chassis QJF, Q6F, A8F, A7F, A6F, S8F,
S7F and S6F.
"Low A, S and M Logic" (LAS) DI523 contains the logic at the least
significant ends of the A, S and M registers up to and including bits A,
■16
S, and M,„. Gates, selectors and some of the low A and S end connection log
ic are shown. The standard base k pseudo adders and the low A and S special
adders appear in "block form. This logic is physically located on chassis Q5R,
A6R, A5R, S6R and S5R.
"Standard AAdder Logic" (STA) D1265 includes two standard base h
pseudo Aadders with their carry inhibit (Kl) gate. These adders were not
realized with basic logic elements throughout. Consequently, open arrowhead
inputs to AND and ANDOR complexes denotes diodes instead of transistors.
The logic shown on this drawing is located on the A chassis of a standard
MAU bay.
"Standard SAdder Logic" (STS) D1266 shows two standard base k pseu
do Sadderso The comments concerning the logical symbolism on the STA drawing
also apply here. The adders are physically located on the S chassis of a stan
dard MAU bay.
"High A and S Special Adder Logic" (HAD) DI526 illustrates the spe
cial adders at the most significant end of the A and S registers. Generally
speaking, these adders are special variations of the standard base k pseudo ad
ders. Carry signals (c, d. , x. , y. ) to the next higher base k pseudo adders
are not needed and therefore are not generated. Because of the fanout required
for the division predictors, alogic and circular shift connections, the out
puts contain amplifiers and cable drivers that are associated with the standard
adder outputs. The high S adder also provides a partial sum over the bits S ,
S_ , and S . Chassis A7F and S8F contain the high Aadder logic, while chassis
S7F and A8F contain the high Sadder logic.
"Low A and S Special Adder Logic" (LAD) D1212, shows the special ad
ders at the least significant end of the A and S registers. These adders are
considerably different than the standard adders. They were realized with basic
logical elements throughout, and must generate two stored carries as opposed to
IT
a
one stored carry for a standard adder. The latter requirement is a consequence
of the fact that the complement carry (ca, cs) appears as a unit in the teh
position. This means that four units may have to be added in the hhfh position
without violating the adder relation. The significance of this will be dis
cussed later. The low A adder must also send information to the roundoff
logic and multiplier recoder logic, Chassis A6R and A^R contain the low A
adder logic, while chassis S6R and S5R contain the low Sadder logic.
"Carry Generator Logic" (CG) D1099 contains the logic used during
the assimilation of all stored carries in A. The carry generator has the bits
of A and the roundoff, P, as inputs. It produces a carry word as described
earlier. When the carry word is added to A via KgA, the output of the Aadder,
, is the assimilated form of A. The stored carries a* which are generated
during this addition are forced to zero by the carry inhibit signal, KI, which
is (negative voltage) during the time KgA is active (i.e., KgA = 1 so that the
carry word is added to A in the Aadder). The carry generator logic is distri
buted throughout the A chassis level of the MAU as indicated by the drawing.
"Standard Q and R Logic" (SQR) D1706 contains a standard Itbit cross
section of the Q and R registers with their associated gates and selectors.
R ■ MgM and R v MgM gate logic also appears. The Q level chassis of a standard
MAU bay contains the logic shown on this drawing.
"High Q and R Logic" (HQP) D1525 illustrates the logic at the most
significant end of the Q and R registers down to and including bits Q^ and R^.
In addition to the standard gate and selector logic, most of the high Q and R
end connection logic appears on this drawing. The latter includes the Q and
R one digit assimilators and the logic which modifies the contents of R on the
way to OUT during S9 of the store sequence. The logic shorn on this drawing
is physically located on chassis Q7F and Q6F.
18
"Low Q and R Logic" (LQR) D152U shows the logic associated with the
least significant end of the Q and R registers up to and including bits Q_„
and Ro 7 « A large part of the low Q and R end connection logic as well as the
standard gate and selector logic appears on this drawing. The borrow subtract
er logic which is used during the generation of quotients is shown in block
form. Part of the logic which forms the inputs to Q> p and R. is shown. These
bits are mode bits during multiplication, but act as carry and borrow bits re
spectively during division. The logic used to overwrite the bits in R^ Q ^ R,(V
R, , R, , R, and R, , with the bit in ES during the RESgFO gate of an SEX or
der also appears on this drawing. The logic shown on this drawing is physical
ly located on chassis Q^R, Q5R, Q6R, BUC, B^C, and B6C.
The "fi and 9 Decoder Logic" (10D) DI506 contains the decoder logic
which is used to set the MsA and MsS selectors during multiplication and addi
tion. The u decoder is used during multiplication only. The outputs of the
(iMsA logic set the MsA selector to either 2MsA, MsA, OMsA or MsA when acti
vated by a command (negative voltage signal) from control point M3 or M5 of the
multiplication sequence. Bits R, , R. and R, which hold the next base 4 mul
tiplier digit and the mode bit form the inputs to the uMsA logic. Bits Q, ,
*
Q and Q, are inputs to the uMsS logic. Its outputs set the MsS selector to
either 2MsS, MsS, OMsS or MsS when activated by a command from control point
M2, Mh or M6 of the multiplication sequence. The U decoder is located on
chassis Q6C The 6 decoder uses the outputs of the (h\ and (HL status memo
ry elements as its inputs. When its outputs are activated by the add QC) or
clear add (Bj sequence, the 0MsA logic sets the MsA selector to MsA or MsA
while the SMsS logic sets the MsS selector to 2MsS, MsS or 2MsS. Chassis Q8C
contains the Q decoder.
The "Division Predictor and a Logic" (DPa) DI507 contains the logic
and memory elements associated with the mechanism for predicting and recoding
19
the quotient digits and the socalled cnlogic < Utilization of the predictor
logic is restricted to the division (d) sequence. The pMsA logic uses the
outputs of the Sadder {o_^> o_n> o_> > ay o > a, and cr ) as inputs. Its out
puts set the MsA selector to MsA, OMsA or MsA when activated by a command from
D7 or D10 of the divide sequence. This same command causes the quotient digit
which vas predicted on the previous step (2, 0, 2) to be transferred from the
t t
memory element G, and H. to the memory elements G.. and H . It also gates the
quotient digit predicted on this step (1, 0, l) into G and H . The outputs
of G! , H, , Gp and H p are fed to the quotient digit recoder as shown. Its out
puts are then transferred to R. p R. _, and R.. » The pMsS logic uses the out
* *
puts of the Aadder [a, , OL , a, , OL , OL , and a ) as inputs. When activated
by a command from D9 or Dll of the divide sequence, its outputs set the MsS
selector to 2MsS, OMsS or 2MsS. This command also gates the quotient digit
(2, 0, 2) predicted during this step into G, and H. . The alogic has Cfov,
ocnz, no; and no; as outputs. These outputs are unreliable unless the MsA se
lector is set to KgA and sufficient time has elapsed for the Aadder outputs
to settle. These outputs Indicate whether the assimilrted value of A is over
flowed, nonzero, normalized or almost normalized. The DPa logic is located
on chassis A8F, A7F, S8F, STF, and A6c.
The "Special End Connection Logic" (SEC) D1527 shows various blocks
of logic associated with the shift (V), floating addition (T), and division (ly
sequences. The A and S normalization logic is used by the shift (f) sequence to
determine overflow during left shifts. The M and R normalization logic is used
by the division fin sequence exclusively. The M normalization logic is used to
determine whether the divisor is normalized at the start of a divide order.
The R normalization logic is used to determine when the generated quotient ap
pears normalized. The sign comparison logic is used only by the division (d)
sequence. Its purpose is to compare the true sign of the partial remainder
20
in A with the true sign of the divisor in M. The result of this comparison may
influence the quotient digit that is inserted in Rl q > Rj ,, and R, j . The Q and
R halfsubtractors are used only in case 3 of floating addition. The carry
borrow logic is used in case h of floating add (a) and for quotient roundoff
in the division fin sequence. Each block of the SEC logic is physically lo
cated on the chassis indicated by the drawing.
The "Zero Detect and RoundOff Logic" (ZDR) D1505 shows the logic
used to detect the presence of all zeros in Q, R or S. It also shows the log
ic used to obtain an unbiased roundoff of A. The output of the roundoff
logic, p, is always zero unless the roundoff status memory element (RO) is
set in the true state, in which case p may be or 1. Note that p is fed to
the low end of the carry generator. The zero detect logic is distributed
throughout the Q and S levels of the MAU. The roundoff logic is located on
the Q7F chassis.
31.2 The MAU Bit Path Logic
The bit path logic for the MAU is displayed on six drawings. The
standard bit paths are shown on SAS (D1707) and SQR (D1706). The nonstandard
high and low A, S and M bit path logic is shown on HAS (D1522) and LAS (D1523)
respectively. Likewise, the nonstandard high and low Q and R bit path logic
is shown on HQR (DI525) and LQR (DI52U) respectively.
The description of this logic will be register and selectororiented.
Equations for the most significant, standard, and least significant bit paths
are given for each of the five registers and six selectors of the MAU. The
connections with the IN(Fl) and OUT(FO) registers of Flow Gate Memory are also
included.
■21
3.1.2.1 The Fl to M Path
As shown at the top of HAS, SAS, and LAS drawings, the Fl. input to
M. is the i — output of the Fl flow gate register. This output reflects the
contents of the Fl. memory element at all times. It is transferred to M. when
1 1
ever the FlgMEM gate is on, i.e., whenever FlgMEM =1. On the top of HAS, note
that Fl n is stored in "both M and M , thus duplicating the sign hit of the in
coming fraction.
31.2.2 The R to M Path
The logic associated with this path is shown on the top of HQR
(D1525), SQR (D1706), and LQR (DI52U). It is used to OR or AND the con
tents of R to M, leaving the result in M. If both the OR and AND are per
formed, R is simply transferred to M.
R ^ M can be done by gating r. to M. if r. = 1, but leaving M. un
changed if r. = 0. R • M can be performed "by gating r. to M. if r. =0, but
leaving M. unchanged if r. = 1. The Boolean expression for gM. is given be
low.
gM. = r (R v MgM) v r. (R • MgM) 1 < i < kh
It is clear from this expression that R v M is performed when
R n/ MgM = 1, and R • M is performed when R » MgM =1. If R ^ MgM = R * MgM =
RgM = 1, the contents of R are transferred to M.
3.1.2.3 The M Register
The M register may be loaded as described in the two preceding sec
tions. Its outputs feed the MsA and MsS selector logic as discussed in the
two sections which follow. Its most significant outputs, m and hl, feed the
carryborrow logic described in section 3«1«13« The m n signal is also used
22
in the conditional logic of A12 in the add control sequence as shown on DI269.
The m , itl and m signals are inputs to the M normalization logic described in
section 3«1«10. The least significant bit, m, , , is gated into the most signi
ficant Felement of the EM register, El^L, during El step of the exponent arith
metic sequence. This is discussed in sections 32 and 5.6.
3.1.2.U The MsA Selector
The MsA selector logic appears at the top of HAS, SAS, and LAS. It
accepts the true and complement outputs of the M register as its inputs. Its
odd outputs, b (i even), feed difference amplifiers, l' L /yj)> wnose outputs
feed the A adder. Its even outputs, b., feed the fifth level of the carry gen
erator as described in section 3«1»8. The outputs of the carry generator, b.
(i even), feed through difference amplifiers to the A adder. The inputs to the
A adder are shovn at the bottom of HAS, SAS, and LAS.
Let i = 2j and < j < 22. The odd and even outputs of the MsA se
lector are then defined as follows:
b. . = m. (2MsA) v m. _ (MsA) v m. _ (MsA)
ll 1 ll ll
t _
b. = m. _ (2MsA) v m . (MsA) v m. (MsA)
1 l+l ' 1 v ' 1
b. = b! v k. (KgA)
1 1 1
1
When j = 22, m. = m, = so the expression for bi 1 is modified accordingly.
The k. signal is one of the 23 outputs of the carry generator added
to the contents of A to assimilate the stored carries and roundoff bit, p,
when KgA = 1. The assimilated value of A or A rounded appears as the output,
QC, of the A adder when the MsA selector mechanism is set to KgA. Since the
selector mechanism can only be set to one option at any time, KgA = 1 implies
23
_ t
that 2MsA = MsA = MsA =0, and hence b. = 0o When the mechanism is set to OMsA,
1
none of the options are active and b~ . , = b_ . =0 for < j < 22.
2jl 2j 
3.1.2,5 The MsS Selector
The MsS selector logic is shown at the top of HAS, SAS and LAS. Its in
puts are the true and complement outputs of the M register. Its outputs, t.,
feed the S adder through difference amplifiers shown near the center of the
three drawings .
The following expression for t. is uniform for all bit positions except
the Urth;
t. = m. ,_ (2MsS) v m. (MsS) ^ m. (MsS) v m. . (2MsS)
1 l+l v ' 1 v ' 1 v ' l+l v '
The expression for t, > is obtained by noting that m. _ = so m, = 1.
The MsS selector has the largest number of options and is therefore some
what more complicated than the other selector mechanisms. (See section U„2.)
Suffice it to say at this point that to achieve t. = for all i, Delayed Con
trol must request either OMsS or KMsS, depending on the previous setting of the
MsS mechanism. If 2MsS, MsS, MsS, or 2MsS was the previous setting, OMsS is a
valid clear request from DC. This is true even though CS may have been prev
iously requested with MsS to accomplish the NOT instruction. If MMsS was the
previous setting, meaning that MsS = MsS = 1, and CS = 0, then DC must request
KMsS to obtain t. = for all i.
1
3.1.2.6 The sA Selector
The inputs to the sA selector logic appear at the bottom of the HAS, SAS,
and LAS drawings, and are generally the outputs, o and 0. > of the S adder.
2k
However, variations occur at the high and low ends of the A register as shown
on HAS and LAS respectively.
A 2J _ X = a 2 ._ 3 dASsA) v a2 ._ x (SsA) v ^ (USsA)
A 2j = a 2j2 ^ASsA) v ° 2 j ( SsA ) v ° 2 j+2 (I ' SsA)
A 2j = °2j2 (1 / US£A)  4j (SSA) V a 2j + 2 ^ SsA )
< j < 21
A U3 = a Ul (V^SsA)  a U3 (SsA) v/ p_ 1 (dl) (1+SsA)
\k = °k2 (V^SsA)  a kh (SsA)  p (dl) (USsA)
A kk = a U2 (V^SsA)  a ^ (SsA)
If OSsA is set, l/USsA = SsA = i+SsA = as usual. It must be pointed
out that DC does not request an sA option alone. Instead, it requests an sAQ
option as described in section U„2. The sAQ selector mechanism interprets this
combined request and activates the appropriate sA and sQ options.
Except for q and c ) the o variables in the above expressions are the
outputs of the S adder as discussed in sections 3»1°3> 3°1<>^> and 3°1°5° The
p , and p signals are outputs of the R onedigit assimilator as discussed in
section 31° 6. If R Q contains a zero, r Q = 0, p = r and p = r_ . The dl
signal has unit value when the DL status memory element is true. When DL is
true (i.e., set to "1")? a double length (meaning A,Q or S,R). left shift is
possible. When DL is true, dl = and only single length (meaning A or S)
left shifts are possible. It is clear from the above equations that A, and
Aii are set to zero when a left shift is performed with' dl = 0.
The logic used to form o ? and a p is shown at the left edge of the HAS
drawing.
25
a_ 3 = (s_ 1 ^ t_ x ) (cr) (S) v a _ 3 (cr) v s a (d)
i
a_ 2 = (s_ 1 v t_ x ) (cr) (5") ^ a _ 2 (cr) v s a _ 2 (d )
The cr and d signals are the true outputs of the CR and V status memory elements
respectively. The a o an< ^ cr 9 signals are the outputs of the R half subtr actor
as described in section 3«l«12o The sq 3 and Sq p signals are the most signif
icant outputs of the high S special adder as discussed in section 3°1°^«
We now analyze the bit configuration at the high end of S to establish
a basis for some of the associated Boolean expressions. Since the S register
includes S , S , and S , it may contain numbers
I4.I1 22
s . 8s a + Z s.2" 1 + Z s* 2 _2k
" 3 i = 2 x k=l 2k
32
in the range 0 < s < ~ where the binary point lies between s_ and s as usu
al. Wc note
■* «
s = 8s „ + Us „ + ks „ + 2s , + s
waere
^ . 22
1 v i y * 2k
= L s.2 + L s 2
i=0 X k=0 2k
If s _ is assimilated over s and s , we find
s = 8(s_ 3 s_ 2 s_ 2 ) + Ms_ 2 ©s_ 2 ) + 2s_ x + s
provided 8 < s < *r. If we now require
26
2
( s _3© s 2 S 2^ = ^ S ® s 2^ = S l
(A)
then 2 < s < r. If instead we require
(s_ 3 ©s_ 2 s_ 2 ) = (s_ 2 ©s_ 2 ) ^ s_ x
(B)
, h lk
then 4 < s <  or 2 < s < — . In the following table, we let A = 1 and
B = 1 imply the truth of the statements A and B as given above. Note that the
*
adder relation, s ,s =0, rules out four cases.
S 3
S 2
*
S 2
s r
, A
B
1
1
1
1
 e 
 e 
 1 
 1 
. _  .
  
i
i
1
i
1
1
[
 e 
 i 
 1 
 1 
.. _ _ _
  
l
l
1
i
1
1
 i 
 e 
 1 
 1 
1
  
i
i
1
i
i
1
1
i
i
1
1
 i 
 i 
 1 
 1 
■■   
  
From this we may conclude the following:
1+
1 . If   < s < 2, A is true .
k 8
2. If 2 < s <  or 2 < s < rr, either A or
8 1^
3* If h < s < 2 or  < s < — , B is true.
is true
•27
E jrthermore, s represents all assimilated bits to its left when A is true, but not
when B is true. Thus, s_ 1 always represents all assimilated bits to its left when
L.
3<s<2.
If we assume s represents the assimilated bits to its left, a right
shift into A or A,Q should place a_ 3 = a_ 2 = (e^  t_ ± ) in k_ ± and A Q as justified
in the next paragraph. A careful examination of the DC Flow Chart (D1128) will re
veal this assumption must be valid during the following control steps: A10 for ca
ses 2 and h of floating point addition, F2 for both logical and arithmetic right
shifts, and the M3 and M5 steps of the multiply sequence. In all cases, the Aadder
output, a, is shifted right into S with S* 2 set to zero prior to the step which
right shifts the Sadder output, c, into A. Since 1 < a < 1 is true initially, it
follows that 3 < OL = a + 2m < 3 and  J < s = £ < \ . The latter range is well with
in   < s < 2. so s must represent all assimilated bits to its left.
3 ' 1
To justify a = a =s^t,we consider the stored carry summation
in the 3 and 2 positions. Note in section 3.1.^ that a* 2 is formed in the same way
as the stored carry output of a standard base h pseudo adder as described in section
, © t 3 (s ^ s _i t _i )
3.1.3.
'>_ 2 = ^_ 2 *■) _ 2 37 v_ 2  _!_!•
x_ 3 = (s_ 2 ©t_ 2 )(s* 2  s^t^)  s_ 2 t_ 2
a = s © t + x
r that t . = t = t_ 1 and we have shown above that s_^  s_ 2 = s_ 1
with s* = in the case of interest. Consequently, we have:
°2 = S l + *l +) "l^l = ""I V *"1
x_ 3 = (s_ x +)t_ 1 )(s_ 1 t_ 1 )  s^t^ = s^t^
o
3
s l® t l © s l t l = s l v t 
1
In case 3 of floating addition, the augend (subtrahend) must be shifted
:ularly left uni I I ^ s exponent is decreased to the value of the addend (minuend)
■28
exponent. To accomplish this, CL is set during the initial pass through A9 of the
add sequence which permits OL — > R^ , a — > R>, and o — > <fy _, a — > Q^ .
Thus, the most significant bits of the augend (subtrahend) are placed in the least
significant bits of Q and R before the addition (subtraction) occurs. When it does
occur, the sum (difference) is shifted circularly right until its exponent agrees
with that of the augend (subtrahend). A carry or borrow may be propagated to the
left during this circular shift. To accomplish this, CR is set during the appro
priate pass through A10 causing a = o and a = a to be placed in A and A .
Likewise, cr = 1 causes a, = oc and a = a to be placed in S and S . The
r t it
a and o signals are outputs of the R halfsubtractor, and the a and a
signals are outputs of the Q halfsubtractor as discussed in section 3.1.12
The V status memory element is set during store clear type instructions
(STC, ASC, SSC), during SAL and SEX, and during the correction of the remainder
for quotient roundoff during the divide sequence. The uses of V during store
clear and divide are explained below. The use of V during the execution of SAL
or SEX is explained in section 3.1.2.12.
At the beginning of a store clear type instruction, the accumulator
contains the result of an addition or subtraction in the case of ASC or SSC and
the result of the previous order in the case of STC. In all cases, the accum
ulator is normalized, A is rounded and stored, and Q, is corrected for roundoff
and placed in A. It is the last step which requires that o = so and
a = so . The signals so and so are defined in section 3.1.^.
The roundoff bit, p, is placed in S and S during the SI step which
also places Q in S and sets V. Since Q, is always considered positive, its sign
bits, which appear in S and S at this point, would ordinarily be zero. If
1 p = 1, a unit must be subtracted from the 2 position of Q to correct for the
th
I unit added to the hk — position of A. This is easily accomplished by making p
29
the sign of Q> When Q is in S, this amounts to making s__ = s p = p* During
the following right shift into A with the MsS selector set to OMsS, s > A
and s > to A~ . OMsS insures that t = so that so = s _, and sg = s
as discussed in section 3'1«^» Since CR and V are true, g = Gg and g = s o
are placed in A and A n respectively during S10.
At the end of the iterative portion of divide the shifted remainder
is placed in S during the final pass through Dll. The hits in S , S , and
S are significant, and must be partially assimilated and shifted right into
A during Dl4. Since OMsS is set in D13, the sg , sg , g , a , and g outputs
of the high S special adder represent a partial assimilation of the bits s ,
s , s , s , , s and s~. (See section 3»1«^«) Since CR is set to "0" and Vis
set to "1" in D13, a = Sg and a  sg are placed in A and A respect
ively during DlU.
3.1.2.7 The A Register
With one exception, the inputs to the A register are the outputs,
*
A. and A. , of the sA selector as shown on the bottom of the HAS, SAS, and LAS
11
drawings. These outputs are gated into the A register whenever gA = 1. The
A , Felement is an exception in that it has two inputs, A and a„. The a„
signal is gated into A whenever a^gA = 0. A zero signal is used since the
input and grounded base of the gating difference amplifier have been reversed 
hence the solid dot gate symbol. This gate is used at the end of the (5) and (F)
sequences during logical operations to insure that A does not appear overflowed
at the entrance to the (Resequence ,
The outputs of the A register feed the A adder and the carry genera
tor. The former is discussed in sections 3»1»3> 3»1«^> and 3°1«5« The latter
is described in section 3°1»8»
30
3.1.2.8 The sS Selector
The inputs to the sS selector appear at the middle of the HAS, SAS,
and LAS drawings. In general, they are the outputs, a. and a. of the A adder.
1 1 >
Variations occur at both the high and lov ends as shown on the HAS and LAS draw
ings.
Except
\ = p (AsR) v a (4AsS)
s_ 2 = p (AsS) v a Q (UAsS)
S 2 = a * (UsS)
S 2j1 = a 2j3 UA ASS) V «2J1 (QSS) V a 2j + l (UASS)
S l = a l ^ ^ k AsS ^ V q i ^ QsS ^ v a 3 (^AsS)
S 2j = °2j2 (1 ^ AsS) V ^J (QsS) V a 2j+2 (UAsS)
S*. =a*.„ 2 (lAAsS)^a*.. 2 (UsS)
< j < 20
S U 2 = a U0 (1 ^ AsS) V %2 (QSS) V ^ (UASS)
s l+ 3 = a Ul (1//4 AsS) " %3 (QsS) " v l (dl) (UAsS)
S UU = ^2 (1 / U AsS) " ^ (QSS) V V (dl) UAsS)
C = °£ 2 (lA ASS)
If OAsS is set, l/U AsS = QsS = ^AsS = 0. As in the case of the sA
selector, DC does not request an sS option alone. An sSR option is requested
31
and the sSR selector mechanism activates the appropriate sS and sR selector op
tions as described in section U.2.
In the above equations, the a signals are the outputs of the A adder
except for a, _ and a which are discussed below. The roundoff, p, is used
to set the S and S Felements whenever AsR = 1. This is of no consequence
except during store clear type instructions as explained previously in section
3.1.2.6. The q signals are the true outputs of the Q register including q^p
*
The latter must be sent to S> during the D17 step of the divide sequence in
order to assimilate a stored carry that may be held in the quotient when a neg
ative quotient digit is anticipated but fails to arise before the division ter
minates. (See sections 3°1«17 and 5°13°) The v , and v signals are the out
puts of the Q one digit assimilator as described in section 3«1»6. The dl sig
nal is the true output of the "double length" status memory element, DL, which
must be set to "1" to permit double length shift operations in the accumulator.
The Ot and a signals are formed by the logic shown in the lower
left hand corner of the HAS drawing.
»
a = (sa)(cr)\ v a__(cr)
a_ 2 = (sa)(cr)\ v a_ 2 (cr)
sa
= b_ 1 ^ a _ k v a_ k 1 (SsA)
The cr and X signals are the true outputs of the "circular right," CR<, and "log
ical," A> status memory elements. The a „ and a signals come from the Q half
subtractor as described in section 3.1.12. The k , = a K (KgA) signal is in
10
section 3*1°8. The SsA signal is obtained as shown on the HAS drawing. SsA =
whenever the sA selector is set so that gA = 1 causes a. — — > A. .
The original expression for sa was incorrect. The error was detected
32
by the Snyder program as described in File No. U8l by J. N. Snyder, D. B. Gillies,
R. D. Hill, and P. G. Kruger. The logic shown above is correct and is currently
in use.
When CR, A, and l/^AsS are true, sec must represent all bits to the
left of a, with or without KgA = 1. (KgA = 1 means that the MsA selector is
set so that the output of the carry generator is added to A causing the A adder
output, OL, to represent the assimilated value of A.) In this sense, sot plays the
role of (s , v t , ) as discussed in section 3»1«2.6. Its function is complica
ted by the fact that A may be assimilated during the right shift into S. In any
case, S . and S~ must represent all assimilated bits to the left of S , after
the right shift is complete. S and S are always set to zero in this case.
The sa signal is gated into the S and S~ Felements during the fol
lowing control steps: A9 in cases 2 and k of floating addition; Fl during arith
metic right shifts that arise in the execution of STF, SIF, SEQ, or SIA; Kl if
A is overflowed in the twos complement sense or if it appears to be zero; MU and
M6; and D6. KgA is set during Fl, Kl, and D6 . Generally, KgA is set. during A9
unless d = 1 in which case the 0MsA decoder controls the setting of the MsA
selector as discussed in section 3«1»1^« The uMsA decoder controls the setting
of the MsA selector during Mk and M6 as discussed in section 3 •1*15* so KgA = 0.
When KgA = 0, sa is logically equivalent to (s ^ t ). We shall
consider this case first before attempting to explain the more difficult situa
tion when KgA = 1.
During the first pass through A9, we are guaranteed that 1 < a < 1
in case 2 or k of floating point addition. The initial steps of the multiplica
tion sequence guarantee that l/2 < a < l/k during Mk. Furthermore, the stored
carries of A are guaranteed to be zero during Mk. During M6, the worst case
limits on the contents of A are: 2/3 < a < l/3« Using the results of section
3.1.2.6, we know that a represents all assimilated bits to its left when
33
U/3 < a < 2, and hence during A9, MU and M6
*
We can now show that sec = a , ^ b . Since a _ is formed in the same
a standard base U pseudo addition over the bits to the left of a (See sec
manner as any other stored carry output, the a _ and OL p signals should represent
a standard base h pseudt
tions 313 and 3.1A. )
a . 2 = a 2 ® b 2 ® ^ a 2 V a l b l^
c _3 = ( a _2 © b 2^ a 2 V a l b l^ V a 2 b 2
« 3 " a  3 © b  3 © = 3
Since a _ = a p = a . and b = b_ ? = b , the above equations reduce
to a . = a_p = a , v b_ . In both case 2 and U of floating point addition, the
shift after the addition, a + m, is to the right into S during A9 followed by
a left shift into A with nothing added during A10. Thus, even though we cannot
always assume b=b=b in case k addition, the bits inserted in S and
S„ during the A9 step are lost during A10.
This was not a problem with the S to A path as discussed in section
3.1.2.6. The shift following a case 2 or k addition from S is always straight
into A. A discussion of the peculiarities of case k addition is given in sec
tions 3°1«13 and 5.5.
Examination of the DC Flow Chart reveals that KgA = 1 during Fl, Kl,
and D6. The correct overflow and detect zero sequence [KJ insures that
1 < a < 1 during Fl and D6. Therefore, a , represents all assimilated bits to
its left. The true sign of A is a k where k represents the carry into
the 1 position as defined above and in section 3«1»8» Since KgA = 1, b =
*
and ou. = for 1 < j < 22. Furthermore, a .. = a , © k _ . It follows that
2j  °  '11^1
a _3 = a _p = a i =a©k =sa during Fl and D6.
3U
A little more care must be exercised in determining the expression
for sa during Kl. Since KgA = 1, the assimilated contents of A are shifted right
into S. The sa signal is used to set S and S Q , and should therefore represent
the true sign of A. So long as 2 < a < 2, it is clear that a = a , ©k is
the true sign of A and so: = a , © k , is perfectly valid. However, if a = 2,
a, = 1 "but sa should be zero .
The Qy, (b), Qd), (f) , (h) , (m) , and [Sj sequences may terminate with
an entry to the (k) sequence. The Kl step may or may not include gating sa into
S and S . We are guaranteed the following about the value in the accumulator
at the entrance to Kl: 1 < a < 1 for (f) and (l); 1 < a < 1 for (d) , (m), and
(s); 2 < a < 2 for A; and 2 < a < 2 for B. Therefore, sa = a_, + k_ x is valid
in all cases except when the CST order is executed with 1 as the operand.
It is much too expensive to detect the case a = 2. Consequently, we
trade precise knowledge of the contents of A for transistors and arrive at a
more subtle solution. The following observation is useful in this regard. If
the sA selector is set to SsA at the entrance to Kl, then except for the entry
from (BJ it is guaranteed that 5/h < a < 5/U. This guarantee also applies at
the entrance to Fl and D6.
Since the above range is well within U/3 < a < 2, a is representa
tive of all assimilated bits to its left. Hence, if k . = 1, a and bits to
its left must have unit value, i.e., a ,k = when ^/h < a < ^/h. The ex
pression for sa = a k can be simplified to sQ  a ,k in this case.
We now show that sa = a , k represents the sign of A when Kl is en
tered from the (b) sequence. If a binary left shift is executed, BLS } k = 1
while a gA insures that a , = a^ so sa = a , , which is clearly the sign of A.
Except for CSB and CST, the other instructions which are executed via the (B)
sequence leave A assimilated, i.e., without stored carries, so k =1 and a
35
represents the sign of A. Both CSB and CST may leave A with a stored carry in
A. at the exit from the (B) sequence. All other stored carries are zero, so
the bit pattern at the high end of A is easily predicted. In fact, a , repre
sents the sign of A in all cases. Note that k , = only when CST is executed
vith 1 as the operand. Since the result is a = 2, sa = a ,k =0 accurately
reflects the sign of A.
In case 2 of floating add the range of the result is 2 < a < 2 if
the exponents of the augend (subtrahend) and addend (minuend) are equal, i.e.,
d = 1. Note that when d is odd, the sA selector is set to l/k SsA instead of
SsA. The sign of A is determined by sa = a , © k _ , The two examples shown be
low illustrate how the sign of A may be + if a , = 1 or  if a . =0.
Initial A + M
Right Shift into S
with KgA =
Left Shift into A
with KgA = 1
A assimilated at
entrance to Kl
{
10
1 1.0 1 1 . . .
0.0 111 . . .
1 x
1 1.1 1 1 1 o . .
1
1 1.0 oo«...
0.0 0....
1
1 CI 1 1 1 .
1 1.0 .
1 x
1 1.0 1 1 1 .
1
1.0 . .
1 0.0 . .
The resulting expression for sa is the one given at the beginning of
this section. When KgA = 0, k , =0 and sa = a v "b . . When KgA = 1, b . =
and sa = a ,k . When KgA = 1 and SsA = 0, b =0 and sa = a , © k . There
fore, the value of sa is correctly determined in all cases.
We now examine the other variables in the equations which define the
sS selector.
When a case 3 floating addition (subtraction) is performed, CR must
■36
be set before the result can be circularly right shifted in A,Q. As explained
in section 3.1.12, a and a are the outputs of the Q halfsubtractor and are
placed in S_, and S during A9. The equations which define a and CC show
that they must equal a „ and a respectively when cr = 1.
The LRS and SRS orders are logical shift orders which treat the assim
ilated value of A as a U5 bit data word (a , a ^kli^ without sign. When a
right shift is performed, zeros are inserted at the left ends of A and S. During
LRS or SRS, \ = 1 and cr = 0, so CC _ = Ot _ = 0. Since KgA = 1 during any pass
through Fl including the first, Ot = 0. The sS equations show that S = if
l/UAsS = 1 and X = 1. It follows that S , S , S , S ,, S^ S Q and S are all
set to zero during the first pass through Fl if LRS or SRS is executed with
l/UAsS = 1. Since CR, V, and OMsS are true during LRS or SRS, the equations in
section 3»1«2.6 show that a ? = o 9 = ®> so A and A are set to zero during
F2 if l/USsA = 1.
3.1.2.9 The S Register
In all cases the S register Felements are set according to the out
puts of the sS selector when gS = 1. The outputs of the S register feed the S
adder (sections 3°1°3> 3«1«^> and 3 1«5)? The S zero detect logic (section
3«1.7)5 and the S normalization logic (section 3«1»10)«
3 . 1 . 2 o 10 The sQ, Selector
The sQ selector logic appears at the bottom of the HQR, SQR, and LQR
drawings o Except for variations at the most and least significant ends, the
inputs to this logic are the true outputs of the R register.
Q_ 1 = o^UARsQ) v p_ 1 (RsQ)  r x (URsQ)
37
Qq = a^dARsQ) v p (RsQ) v r 2 (URsQ)
C* = a* u (l/tosQ)
G^ = p_ 1 (l/URsQ) v r^RsQ) v r (URsQ)
Q 2 = p (l/URsQ) ^ r 2 (RsQ) v r^(URsQ)
Q i = r._ 2 (lARsQ) v r.(RsQ) v r. +2 (^RsQ)
3 < i < 38
Q 39 = ^(l/URsQ) v r 39 (RsQ) v d^RsQ)
Q Uo = r 38 (l/URsQ) v r^ (RsQ)  cL^URsQ)
QL kl = r 39 (l/URsQ) v d^RsQ) s/ r^l+RsQ)
Q U2 = r Uo (l/URsQ)  d U2 (RsQ)  r^(^RsQ)
Q^ = d Ul (lARsQ) >/ r^ (RsQ) v a _ 1 (cl)(^RsQ)
Q uu = d ]+2 (lARsQ)  r^(RsQ) ^ a (cl)(URsQ)
If ORsQ is set, l/URsQ = RsQ = 4RsQ =0. An sQ setting is requested
in conjunction with an sA setting as explained in section U.2.
The q,o> q.j, and m , signals are three of four outputs of the low S
special adder as described in section 3°1°5° The p_, and p signals are from
the R one digit assimilator as shown at the left center of the HQR drawing „
The function of this assimilator is explained in section 3°1°6. The d, and
di _ signals are from the borrow subtr actor logic as shown in detail on the SEC
drawing (D1527). The function of the borrowsubtractor is discussed in section
3,1.17. When r^ = 0, d^ = r^ and d^ = r^ . The CT and a signals are two
38
outputs of the high S special adder as discussed in section 3«1«^» These outputs
are gated into Q._ and Q, « during a circular left shift in case 3 floating addi
tion. It is only under this condition that the "circular left" status memory
element, CL, is set to the "1" state, i.e., cl = 1. Otherwise, a left shift
into Q places zeros in Q, and Q, , .
3.1.2.11 The Q Register
* *
With the exception of Q> p and Q, , the outputs of the sQ selector are
used to set the Felements of the Q register when gQ = 1. The Qk:>Q.m, signal
appearing in the lover right corner of LQR is used to set Qi _ and Q. , to zero
when Q. J^hh ~ ^> otherwise, it has no effect. Q^tQj,k = 1 is true during
all other control steps .
The signal used to set Q, p when gQ = 1 is given below.
* _ _
% 2 ' r U2 ( ^^l ) V ^^Ul) V r U2 r U 3 r ^ 6 2
The first two terms of this expression are part of the oMsA decoder logic which
is described in section 3«1»15« The multiply status memory element, (i, is set
to "1" during the Ml step of the multiply sequence, and is reset to "0" during
the final pass through Mo. Since g p = except during division, Q, = Q, as
defined in section 3«1«15 when i.= 1.
The last term in the above expression is associated with the borrow
subtractor logic as described in section 3«1«17« The divide status memory el
ement, A , is set (i.e., 5 = l) during D10 of the divide control sequence and
reset during DlU. It serves a dual purpose in division as discussed in section
* * t * — —
3"1«17 and 5.13« Since [x  except during multiplication, Qi = Q, = r i,p r ) 1 o r ) i ij.
when 5 2 = 1.
39
The Qii signal sets the Q. i Felement when gQ = 1. It is an output
of the R half sub tractor logic which is described in section 3«1»12. The
kk
*
Boolean expression for Q» , is given below for completeness
Qi hk = (cr)(r U3 )(r^)[r^(OMsS)  s^t^OMsS)]
The Q register outputs feed the sS and sR selector logic (sections
3.1.2.8 and 3»l°2ol2)j the Q zero detector and roundoff logic (section 3°l7)>
the Q one digit assirailator (section 3.1,6)} the nMsS decoder (section 3.1.15 )>
and the Q halfsubtractor (section 3.1.12).
3.1.2.12 The sR Selector
The logic of the sR selector is shown in the middle of the HQR, SQR,
and LQR drawings. In general, the inputs to this logic are the outputs of the
Q register and the A adder. There are variations at the most and least sig
nificant ends of the selector as usual.
R_ 1 = a 13 (o : )(lAQsR) v a_ 1 (AsR) v q 1 ( J +QsR)
R o = a^(?)(iAQsR) ^ a (AsR) v q^UQsR)
R o = o^UAQsR)
R l = V_ ] _(lAQsR) v O^AsR) v q (^QsR)
R 2 = v (lAQsR)  a 2 (AsR)  q^(UQsR)
R i = ^ i _ 2 ( 1 AQsR)  a.(AsR)  q. +2 AQsR)
3 < i < U2
\ 3 = q^UAQsR) a U3 (AsR)  p 43 (5 1 )(^QsR) ^a_ 1 (cl)(UQsR)
ko
R Mi = V (1//1 ' QgR) ~ a l^ Ac n) ~ P[, (BK^QsR) v a (cl)(liQcR)
When OQsR = 1, l/UQsR = AsR = UQsR = as usual. An sR selector option
as explained in section U . 2 .
The a signals are outputs of the A adder as described in sections 3*1 '3*
3>1.^ and 3»1«5« The v , and v_ signals are outputs of the Q one digit assimi
lator which is shown in the lower left corner of the HQR drawing and is discussed
in section 3»1'6. The p, and p, . signals are outputs of the quotient "hit" re
coder as described in section 3«1»17« The 5. signal is derived from the division
sequence logic. As explained in section 3'1«17> B, = 1 during D9, D10, Dll,
D12. (See Divide Control Logic D6D12, D1272.) Since CL and kQjsR are both
true during these control steps, p]_ , and pj, set R. and R, . when gR = 1. CL is
set to "1" prior to the circular left shift in case 3 floating addition to per
mit (X and OL. to set R, and R, . as discussed in section 3 • 1*12. Otherwise,
zeros are placed in R, and R> > when UQsR = gR = 1.
d is the complement output of the V status memory element and is used to
set R and R to zero during the S2 step of the store sequence, This step is
used only during the execution of an SAL (store Q,) or SEX (store exponent) or
der. In either case, Q contains the least significant half of the double length
accumulator. During S2 the contents of Q are shifted right into R. Since all
bits of Q have positive weight, the fraction q , , q_ » . . q, , , q, must be
stored with a positive sign. As Q is shifted right into R during S2, V is set
so §" = 0, causing zeros to be gated into R and R . Note that V is set during
S10 and that d = 1 is always true during all other control steps in which
lAQsR = 1. The V status memory element serves another purpose during the di
vide sequence as explained in sections 3«1»2.6 and 5°13»
4i
jl 2 13 The R Register
Except for R> p and R^j the outputs of the sR selector are used to
set the R register Felements when gR = 1„
\ 2 = ^% 1 % 2 {KeA) v %l%2 {K&k) V %fhh {K&k)] V 5 2 P U2
The term associated with the \i signal is part of the uMsS decoder.
•* * »
When u = 1, 5 = so that R. = R. as defined in section 3l»15« When
*
5 = 1, (i = so Ri = (3, which is an output of the quotient "bit" recoder as
defined in section 3»1«17«
The signal used to set R» > when gR = 1 is defined below. It is an
output of the Q half subtr actor which is discussed in section 3 « 112.
R kh = (cr)(q U3 )(q uu )[q^(OMsA)  a^b^OMsA)]
In addition to the sQ selector logic (section 3°12.10), "the outputs
of the R register feed the FO register and the associated store logic which is
discussed below; the R to M logic (section 3,1.2.2); the R one digit assimilator
(section 31 6) J the R normalization detector (section 3l«10)j the R zero de
tect logic (section 3«l»7)j the uMsA decoder (section 3«l«15)j "the borrow
subtractor (section 3»1*17)» and the R halfsubtractor (section 3l»12).
31 2 lU The R to FO Pat h
The logic in the path between the R register and the FO (OUT) register
is commonly referred to as store logic. It is shown at the top of the HQR, SQR,
and LQR drawings: The inputs to FO are designated as r. When RESp;FO = .i ,
1
is stored in FO •
1 1
r = r r v r i
10 J
r = r l' ^ r r ^ r n
1 1 12 1
i
r =r r i ^ r r ^ r r ^ r n
2 1 J 02 12 2
r.' = r. (3 < i < 38)
i
r. = xr. v x(es_) (39 < i < UU)
i i 7  _
The n, j , and x signals are the true outputs of the N, J, and X status
memory elements respectively. Since RESgPO = 1 only during the S9 step of the
store sequence , the settings of N, J, and X at that time will determine the way
in which R is transferred to FO. X is never true during S9 except when SEX (store
exponent) is executed.
The six store orders which normalize the accumulator before storage
takes place are ASC, SSC, STR, XCH, STC, and STN. For these orders N, J, and
X are true during the S9 step. Therefore, r = r r , r = r r v T i r p>
i i
r = r , r„ v r r^ ^ r, r_, and r. = r. for 3 < i < kk when RESgFO = 1. Normal 
2 10 2 12' l l   u
ization insures that the fraction in A,Q satisfies: 1 < f < l/k, f = 0, or
l/k < f < 1. A and J are true for all six orders so A is rounded during SI.
Consequently, the fraction which is stored may he in the range: 1 < f < l/k,
f = 0, or l/k < f < 1. If f does not equal l/k or +1, then r = r , r, = r
and r = r . If f = l/k, r = 1, r = 0, r = 0, and r. =0 for 3 < i < kk .
In other words, f = l/k is stored as 1, and the exponent is decreased by one
i i t
to compensate in steps S5 and S7. If f = +1, r = 0, r = 0, r = 1, and
r. =0 for 3 < i < kk. Thus, f = +1 is stored as +l/k, and the exponent is in
creased by one to compensate in steps S5 and S7«
The STU, STF, and SEQ orders do not normalize the accumulator but
they do round A on the way to R. J and N are true for STU while J and N are
true for STF and SEQ.
■43
t I
During S9 for STU, r Q = r_ 1 r Q , r ± = i^, r^ = r_ 1 r Q v r g , and
r
i
r
= r. for 3 < i < kk. If 1 < f < 1, r. = r. for < i < kk. If f = +1,
i '    ' i i  '
 0, r, = 0, r^ = 1, and r. =0 for 3 < i < kk. Therefore, +1 is stored
' 1 ' 2 i — —
as +l/U and the exponent is increased by one to compensate in steps S5 and S7«
i
During S9 for STF and SEQ, r. = r. for < i <kk. Therefore, the
rounded fraction in R is stored Modulo 2.
SAM, SIF, and SIA store A or A shifted without normalization or round
off. Since J and N are true for SAM, the store logic between R and F0 behaves
as described for the STU order , J and N are true for SIF and SIA so the beha
vior of the store logic is the same as described for the STF and SEQ orders .
The SAL order right shifts the contents of Q by one base k position
on the way to R and inserts zeros in R and R . J and N are true during S9,
so R to F0 logic behaves as described for the STU order. However, r = r =
in all cases, so it is never necessary to modify the exponent.
The SRM order stores R Modulo 2. J and N are true during S9, so the
R to F0 logic behaves as described for the STF and SEQ orders. This order is
primarily used to store the fractional remainder, r, immediately after a di
vide order. The Modulo 2 store causes no difficulty since r < d/2  , and
the fractional divisor, d, is always less than or equal to unity in magnitude.
The SEX order is used to store an 8 bit exponent in the last 13 bit
quarter word of F0 with the sign bit, es„, duplicated in bit positions F0 ,
F0. „, FOi , FCK p> ^0. , an ^ L F0, » o The signals es^ through es are stored in
FO.  through FO as usual. The overwrite of r through r, , is accomplished by
the logic shown at the top of the LQR drawing and defined at the beginning of
this section. X is true during the S9 control step only when SEX is executed.
For this order the first three quarter words of FO are generally of no impor
tance. As for SAL, V is set to "1" during S2, so R and R contain zeros dur
ing S9» Since J and N are true, bits r through v o are stored in FO Modulo 2.
kh
3 Standard Base h Pseudo Adders
The A and S adders extend over UG and hu bit positions respectively.
They are composed of a high special adder, a series of 21 standard base h pseudo
adders, and a low special adder. The A and S inputs to these adders as veil as
their outputs are in stored carry representation. For a discussion of stored
carry representation and its ramifications, the reader is referred to File 263
by J. E. Robertson and G. Metze.
We now consider the base k pseudo Aadder as shown on the right half
of STA (DI265). Remember that no attempt is made to distinguish signals which
are logically identical but electronically different.
Let a. represent the true output of A. and let b. represent the true
th
output of the MsA selector OR in the i — position (i even). Note that b. de
pends on the setting of the MsA selector. In the list shown below, m. repre
sents the true output of M. .
Selector Setting Selector Output Selector Setting Selector Output
MsA: b. = m.
1 1
KgA : b . = k . ( i even )
b. = (i odd)
1
*
The inputs to the standard base h pseudo Aadder are a. , a.
2MsA:
b = m. _
i l+l
MsA:
b. = m.
1 1
OMsA :
b. =
1
_*
,._ 2 , a. ± _ lf c.,
Since we are examining an Aadder, the carry inhibit
1 ll 111
— *
input (KI) also appears . The outputs of the base h pseudo adder are OL. , OL. ;
— *
OL. , c. , and d. ^ inhere OL. _ is the stored carry and c. _ represents the carry
1 12 12 12 12 *
sent to the adder on the left. The significance of d. p will become apparent
below, The addition performed may be visualized as follows:
1+5
* i ! *
EL l i 6 .
i2  i
! a. , a. i a
i ll i  i+l
l"b. . b. b. .
iI i i i+l
i2  I
il i '
Let c = a, v a . _"b. , and d. = a. . v b . It follows that
j_ 1 1+1 1+1 1 1+L 1+L
QE
t ^®\®^
a = (a.b. v a.b.)a.d. ^ (a.b. v a.b )c.
i v ii 1111 ii ill
The carry into the (il)— position is c^ = a i b i v/ ^(a^ v a.b^. In terms
of this carry and its complement we have
a ii = a ii©Vi @c ii
a ii = (a ii\i v ViVi^ii v (a ii b ii v a iiVi )c ii
The stored carry is formed as
a U  I'wVi  Vl b il )(c ll )(S)
The carry which is sent to the next adder to the left is
C i2 = a I2 v a il b il
For convenience, the partial complement of c. 2 is also formed as
d. _ = a. _ v b
12 il il
Note that the carry propagation chain is broken by storing the carry
hG
*
a. , which nrises to the right of the (i1) — position. The c. carry can only

'i2
arise as the consequence of a stored carry, a. _, or the condition a. n = b. ., =1,
i2 i1 ll
It is important to note that the condition a. p = a. , = 1 can never arise.
This is quickly proven by shoving that a. 1 a.
the adder relation.
0. This identity is called
When KgA = 1 (i.e., when the MsA selector is set to KgA such that
b. equals the k. output of the carry generator if i is even and b. = if i is
odd), the carry inhibit signal KI = 0. It is clear that Ct.  under these
conditions. The necessity of the KI input is explained in section k.2.
A description of the standard Sadder is almost identical. The adder
shown on the right half of STS (D1266) is considered below.
Let s. be the true output of S. and let t. be the true output of the
MsS selector OR in the i — position. The value of t. depends on the setting of
MsS as shown below.
Selector Setting Selector Output
2MsS:
MsS:
OMsS:
KMsS:
m
1+1
t. = m.
i i
Selector Sett
ing
Selector Output
MsS:
2MsS:
t. = m.
l l
t. = m. _
l l+l
MMsS:
t. = 1
i
CS:
t. =
i
— *
s
The inputs to the standard base h pseudo Sadder are s. o3 s
i2' "i1' V
i' t i±> t i' X i' y i° The out P uts axe a ±2' ±V °i> x ±2' and y i2° In this
notation, a . is the stored carry and x. is the carry transmitted to the
adder on the left. The significance of y. is explained below.
*
*
S i2
s.
1
s ii
s .
1
s i+l
;v,
t.
1
1+1
*
a i2
i
J i1
■hi
Let x. = s. vs. , t. , and y. = s. , v t. , n . It follows that
i 1 i+I l+l J i l+l l+l
a. = s. © t, © x.
l l w i w l
a. = (s.t. ^ s.t.)s.y. ^ (s.t. v s.t„)x.
u i 11 ill" 7 ! i i ill
The carry into the (il) — " position is
x. , = s.t. v x.(s.t. v s.t.)
il ii i v i i ii
Using this carry and its complement we have
*ii = s ii©Vi© x ii
CT ii = WAi v ViVi^ii v ( ViVi v »i.i*ii )x ii
The stored carry is given "by
q. „ = (s. , t. , ^s. ,t . Jx. ,
i2 il il il il il
The carry which is sent to the adder on the left and its partial complement are
formed as
*
x. = s. v s. .t. .
i2 i2 il il
and
y i2 = S i1 V Vl
These Boolean expressions are identical to those for the Aadder ex
*
cept that a _p is not a function of KI.
3.1.U High Special Adders
The high A special adder is shown on the right half of HAD (D1526)
1*8
Its *e a . , a . , a n , a . . b_ , , I , , , and KI. Its ou
* — —
are a of oc , a ., a n , and a . The Boolean expressions for its oul \ re the
same as those for the standard Aadder with i = 0. Since there is no adder to
the left, c _ and d are not formed. The amplifiers and cable drivers providing
fanout for the a , and a. signals are the only other special features of this adder
The special high Sadder is also quite similar to the standard Sadder.
Its inputs are s_^, s_ 2 , s_ 2 , s_ g , s_ 2 , s _ ± , s_ p s Q , s Q , s Q , x Q , y Q , t_ ± , t_ ± ,
_ _ _ — * —x
t Q , t Q , m_ , m_ , m^, and m . Its outputs are so , so , sa _ 2 ^ a 2 , °2' °l'
— — *
a .j a , and a_. The Boolean expressions for a , a , and a are the same as
those for the standard Sadder with i = The complements of these signals are
obtained with difference amplifiers as shown on D1526. The special outputs
so _, so , and so are used only during division and store orders as discussed
in sections 3 .1.2. 6 and 5.13. None of these outputs were anticipated in the
original design.
The need to include so and so as inputs to the pMsA division pre
dictor was pointed out by R. H. Farrell. The logic used to realize these signals
was valid for all division orders and operands except for an NDV order with an
operand of 1 or a VI D order with a rounded accumulator of +1. In either case
the fractional division is performed with a divisor M = +1. Using the original
logic, this condition gave rise to erroneous quotients whenever the dividend was
such as to cause 2MsS or 2MsS followed by MsA or MsA to be selected during the
division process. This error was first discovered by the group working on a
slightly modified version of the New Illinois Computer at the Weizmann Insti
tute of Science at Rehovoth, Israel. As reported by M. Melman, an NDV order
gave incorrect results when the initial dividend and divisor were 1. This led
to the discovery of other cases. The expressions for so and so shown below
are valid for all division orders and operands.
The so output was created after a division error was detected by
J. E. Robertson's ASMD test routine. The trouble in this case was traced to
U9
the fact that the adder relation a~a = was occasionally violated during the
Dl*4 step of the divide sequence. To avoid this, it is necessary to assimilate
over S , S , and S during the down right shift into A , A , and A when
ever the V status memory element is in the "1" state. (See the expressions
* r\
for the inputs to A , A , and A« in section 3.1.2.6;
It is most informative to develop the Boolean expressions for these
special outputs separately. We shall consider the expressions for sa and so
first.
Since a is formed in the standard manner, the theoretical expres
sion for sa (i.e., the a output in the 2 position) is
sa_ 2 = s_ 2 0t_ 2 ©x_ 2
where
X 2 = S 2 V ^l
The sa signal is used only during the D7, D10, and Dl^ steps of division and
the S2 step of store. Except in D7 and D10, the t. (i = 3, 2, 1, ... ) sig
nals are since OMsS is selected. In the D7 and D10 steps 2MsS, OMsS, or 2MsS
may be selected. The first and last of these options require special attention,
If 1 < m < +1, t = t for 2MsS or 2MsS, If m = +1, t ^ t except when
OMsS is selected. The following expression for t is correct for the three
selector options of interest when 1 < m < +1.
t2 ; t l (m i m O ) v t (m l m ) = t l m l v ^O V VA
This expression is clearly incorrect if we were concerned with the MsS or MsS
selector options. In that event it would be necessary to replace t_ with t
in the above expression. Since the MsS and MsS options are never used in con
junction with the sa signal in the present design, the availability of the
50
t signal as compared with the t signal argues in favor of the above expret;
Therefore, sa and so are formed as
s °_ 2 = t s _ 2 X 2 vs 2 X 2 ] © t ^
S0 2 = [s 2 X 2 V S 2 X 2 ] ® t 2
The term in brackets is called cy on the HAD drawing. By using the restoring
EXCLUSIVEOR and EQUIVALENCE circuits we avoid forming t and insure the proper
voltage level for sa and sa _ as inputs to the division predictor. The carry
signals x and x are formed in the standard manner as shown on STS (D1266).
We now consider the sa signal. This output of the high S special
adder is not equivalent to the a. output of a standard Sadder except when
OMsS is selected. However, OMsS is the selector option when sa _ is used in
steps T)lk and S2. The theoretically correct expression for sa is
^. 3 = b_ 3 © t_ 3 © x_ 3
where
x _ 3 = s . 2 t 2 x_ 2 (s_ 2 @t_ 2 )
and
X 2 = S 2 " ^l*!
Since t. signals are in the cases of interest, this expression can be simpli
fied to
sa = s @ ky
where
ky = s_ 2 s_ 2
.51 UNIVERSITY OF
ILLINOIS LIBRARY
3«1«5 Low Special Adders
These adders were designed for the least significant base k digital
position of A and S. The following bit configurations must be examined in
this position.
* J
* i
%2
%h '
a U3
%h '
b ^3
ca 
a
U 2
a
a
hk
a,
k3 "kh
L l
*
«0
S U2
*
*
r o
S h 3
S kk
r l
r o
\i
cs
°k2
o.
*
i+3 °kk
The variables q. and r. represent the true outputs of Q. and R. . Bits
11 11
(ca) and (cs) are the complement carry bits which must be added in the Im
position when doing a subtraction of M or 2M from A or S in complement arith
metic. It was noted earlier that ca = 1 when the MsA selector is set to MsA,
and that cs = 1 when the MsS selector is set to MsS., 2MsS, or CS
The low special adders are designed such that the adder relation is nev
er broken within the limits of A and S provided a^ = s, < = prior to a subtrac
tion and left shift) and such that a carry can never arise from Q or R, i,e»,
q_,q q = r , r n r = 0. A subtraction followed by a left shift can only occur
in division during the transfer from A to S. The subnormalization step prior
to the iterative loop of divide sets a> i = and therefore precludes the possi
bility of a broken adder relation within the limits of A and S. The adder rela
* *
tion may be broken between a* . and q or s, , ■ and r ; however, this is of no
concern, since the second restriction prevents a carry from propagating into the
kb — position from Q or R.
■52
, nth
The cases of interest are those involving four units in the 44 — position,
The outputs of the special adders in each of these cases are shown below.
*
& 44
a U3
\h
\3
ca
%2
*
a U3
a kh
(1)
1
11
I 11
1 1
1
00
(2)
1
01
01
1
00
(3)
W
i
ii
01
i
i
01
1
01
11
1
1
01
*
%h
s ^3
s kh
%
cs
*
*
°k2
a 44
%3
°kk
■X X
In cases (l) and (2), a i and ™ j, equal as they do in all cases where
th
fewer than four units appear in the 44 — column. In case (l) the two units in
rd
the 43 — column generate a carry input to the standard base 4 pseudo adder over
*
bits 40 , 41, and 42. Therefore, the outputs of the special adder do not re
flect the presence of these two units. In cases (3) and (4) the outputs of the
special adder must represent a sum of six units without violating the adder re
lation. This is accomplished by allowing a stored carry to appear in the 44—
position of the adder output. If a right shift follows the subtraction indi
cated by (3) and (4), the restriction q , q o 0. o  or r ^ r = is clearly
satisfied.
A left shift following either of these subtractions could result in a vio
lated adder relation in S or A. For example, if q , =1 and a, . = 1, then a
left shift into S would produce a
44
> sj^ = 1 and q_ 1
> s, _ = 1 such
43
that SipS, p 0. This is why a« > and s. , must be at the start of any series
of subtractions and left shifts. Since r ,*" r  q %Sif)  0; it is possible
to assimilate q^ or r during the left shift into S or A such that > Si <
or > aii . (See section 3«1»6.) Therefore, the requirement that
53
* *
a> . => s. . = at the start of any subtraction and left shift sequence is suf
ficient to guarantee that the adder relation will not be violated within the
limits of A and S.
If the subtractions indicated by (3) and (h) are followed by a straight
shift into the next register (which must be from S to A), a> ^a •, ^ay n ot be
identically zero. This could cause trouble if it were followed immediately
by a subtraction of type (3) or {k) and a left shift into S. This subtract
shift pattern does not occur in the present realization of Delayed Control, The
general addsubtractshift patterns which do occur are outlined below.
Cases 2 and k of Floating Add S
©
Case 3 of Floating Add
©
General Step of Multiply
®
Last Step of Multiply
5U
General Step of Divide
©
Remainder RoundOff Connec
tion
©
The truth table for the low special adder is shown below. The
Ci _(x, ) function represents the carry into the ^3 — position. The outputs
\^%2^* a ^3^ a l+3^ C U2^ X ^2^ and d U2^ y U2^ are formed in the st an dard manner
*
*
*
a U3 \3
%k
\k
%h
ca
a hh
a kh
C k 3 ^2 a k2
*
*
*
%3 \3
%h
\h
S U1+
cs
°hh
a kh
X ^3
\ 2 (
\2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
,,
'
1
1
1
1
, 1
/ \
/
1
1
1
1
c
) ]
1
1
1
1
1
1
1
1 (
) ]
1
1
1
1
1
1
1
1 (
) ]
1 ]

1
1
1
1
(
) ]
■55
The a outputs may "be expressed as follows:
a kk = ki, a ikV ca)
'[>3®v]
a kk " \\k®\k®%k® ca \
% 3 = % 3 ®\ 3 ®% 3
[ a lA a wV (ca) J " i
% 3 ®\ 3
OL
k2
C:
^3
% 3 ®\ 3
\h @ %h
\ 3 ^ %h%k\h ica)
\k v ca
* —
t
v %h%k\ \h v ca
' I a i^ a ^V (ca }
' a 44 b M^ ca )
% 3 ®\ 3
Note that unless a. > a< Jd, , (ca) = 1; the special adder performs the same function
as a standard base k pseudo adder «
The logic used in the physical realization of the low A special adder
is given below. It is in agreement with the logic shown on LAD (D1212).
oc
kk
a uiAiiV ca)
\ 3 \ 3  % 3 \ 3 j
a
kh
_* _ *
v/ a
hk
a
'43
a
U2
'43
U ) 0(\ u  ca) (b uu  ca)
©<4 3
#
[% 3 \ 3 N ' a 4 3 b 4 3 J (c 43 )(Kl) " a UU a UU b UU (ca)
«t ^. x. ,
(%k%h " a UAU )( \u v ca) v a 4>AU ( V v ca) v a uu b W
a 4 3 \ 3 v a 43 b U 3
v a Ul+ a ^ b ^ (ca)
a j 43 \ 3 ^ a 4 3 \ 3
'42
a 42 V a U2 b U2
d U2 = a 4 3 v b U 3
— *
Note that KI does not appear in the expression for a. , since b. . = when the
MsA selector is set to KgA.
The expressions for the low S special adder are obtained by making the
following substitutions: a = 0L } x = c, y = d, s = a, t = b, and cs = ca. The
— *
KI variable does not appear in the expression for u. .
3.1.6 One Digit Assimilators
The Q and R one digit assimilators are shown on the left side of the
HQR drawing (DI525), They each consist of a two input OR and a two input AND,
Their function is to assimilate the stored carries which may appear in Q and
R»„ This is necessary for two reasons. If a left shift occurred without assim
ilation^ the adder relation might be violated. If a right shift occurred with
out assimilation, Q. and R. memory elements would be needed.
A subtraction of M from S followed by a right shift maps a, into Q„,
hk = X and %
(See section 3.1^2,10,) If the subtraction is case 3 or h } 0,1 =1 and Q, = 1
following the shift. This is the only way to set Q = 1. Similar statements
*
are valid for R .
Since there is only one bit configuration for Q, , Q, , and Q, which
u _ 1 , ^ Q ,  ^ Q
= asRirrn'T at.nnn i a ^r&r^r ci'nrnlp TVip rm+.Tm+.
permits Q = 1, assimilation is very simple. The output of the low S special
x
adder is such that if a = 1 following a left shift, then q = 1 and q = 0.
Assimilation yields
and
V.!  <!_!  %
_#
V = %%
For R we have
Pi = r i r o
57
and
P = Vo
If the stored carry is zero in either case, the outputs of the assimilators agree
with the respective bit positions of the Q and R registers.
3.1,7 Zero Detectors and RoundOff Logic
This logic appears on ZDR (DI505). The S, R, and Q zero detectors
are large OR trees. Their outputs SZ, RZ and QZ are zero when the respective
registers contain all zeros,
SZ = S v s_ ^ S n ^ • \s s, _ V Si ,
o 1 43 44
RZ = r . ^ r^ ^ r n ^ ^ r, _ v r n
10 1 43 44
QZ = V_ x  V Q  q x _ U2
where
q i42 = *1 " % ^ """"" %1 V q 42
In order for SZ to he valid, the stored carries must be assimilated „
The same would apply to RZ and QZ with respect to the carries or borrows stored
in the 42 and 44 positions; however, these bits are always cleared to zero at
the time RZ and QZ are inspected. A unit in R n would not cause RZ to give a
false indication, since there would also be a unit in R as discussed in the
preceding section. The formation of QZ is slightly different for two reasons „
First of all, Qi _ and Q, 1 are always cleared to zero during the decode step (Gl)
of any DC instruction and during K3 of the correct overflow sequence, OQ, for
SSC, ASC orders. (See sections 3.1.2.12 and 5.1.) In all cases, the QZ and
roundoff logic outputs are inspected by DC before any units have been gated
■58
into Qi 3 and Qi )• This justifies the omission of qi _ and q,« in the expression
for q, i _. The expression for QZ would be just as valid if q and q^ were used
in place of V and v for the reasons discussed in the preceding section. The
V and v n signals are necessary inputs to the associated roundoff logic, so
it was convenient to use them for the formation of QZ as well.
Note that cable drivers and difference amplifiers are used to distri
bute the true and complement outputs of the zero detect logic. The control
points of the DC sequences which use these outputs are indicated in the "Refer
ence Logic" line of the output table.
The roundoff logic is shown in the lower right corner of ZDR (D1505)
Its inputs are q «_, V . f v , an ©an , and ro. Its output is the unbiased
roundoff bit p.
p = (ro)(v_ 1 ) (a kk ®a kk )  V Q  q ± _ k2
As discussed earlier, p = if the roundoff status memory element
RO is set to RO, in which case its true output ro = 0. Prior to a roundoff
operation, DC must set RO causing ro = 1. In this condition, p may be or 1
as defined above. It is added to the kh — position of the A register as a car
ry into the low end of the carry generator. (See section 3»1«8«)
The roundoff carry and the stored carries of A are assimilated via
the carry generator and Aadder when KgA is true. The rounded and assimilated
result appears at the output of the A adder and is transferred to R in all cases
Following this transfer, DC sets RO to insure that p = 0.
The rules for unbiased roundoff are stated as follows, where the
binary point in Q is assumed to lie to the left of Q .
r if Q < 1/2
[or if a. . © a*, = and Q = l/2
■59
if Q > 1/2
or if a. . © a. . = 1 and Q = 1/2
Since cu = q_ = 1 may occur, it is necessary to use the outputs of
the one digit assimilator v , and m together with q . in determining the
range of Q. The Boolean expression for p given above is seen to agree with
these roundoff rules. Note that a^ © an is formed in the low A special
adder as a^a^ ^ %k%k°
3.1.8 Carry Generator
The carry generator logic is shown on CG (D1099)° It is used in
conjunction with the A adder to assimilate the stored carries in A and the
roundoff bit. The inputs to the carry generator are p and all the hits in A
except a . Because of the manner in which the KgA gate signal is introduced,
the fifth stage of the carry generator logic also includes a part of the MsA
selector OR logic for the evennumbered bits. As a consequence, the b. (i even)
are also inputs to the CG. This is illustrated in the upper left corner of the
CG drawing. The expressions for the outputs of even and oddnumbered MsA
selectorOR s are given below.
b. = ('MsA)m. v (MsA)m. v (2MsA)m f 1 odd
1
b. = b. v (KgA)k.
1 1 ^ 1
>
where ? 1 even
1
b. = (MsA)m„ v/ (MsA)m. v (2MsA)m. .
1 1 'l ' l+l
The flattened OR symbol is used when i is even to indicate that a non
standard OR circuit is employed. The k. signals for i even are the true outputs
•60
of the carry generator even though they are not shown explicitly on the CG draw
ing. Since b. = b. ^ (KgA)k. is accomplished in the fifth stage of the CG, the
outputs shown are the b. . Note that b. = b. when KgA = 0, i.e., when the MsA
selector is set to something other than KgA, However, when KgA = 1, b. =0 and
b. = k. if i is even and b. = if i is odd. The k. as used here does not equal
11 l i
K. as shown on D1099
The K output is used in the sign A and sign comparison logic which
is discussed in section 3«1«H« The k , output is used in the high A bit path
logic as discussed in section 312.8.
Do J, Wheeler designed the original carry generator as described in
Report 92 • Its use permits the assimilation of all the stored carries in A and
the roundoff bit, p, in one pass through the A adder with KgA = 1. To accom
plish this, it is necessary to generate the carry, k. , that is introduced in the
leastsignificant position of each base h pseudo adder when all of the stored
carry bits of A and/or the roundoff bit are added to the noncarry bits of A,
In order to have a carry into the i — position (i even) there must be a stored
carry bit or roundoff bit and a noncarry bit in the (i + j) — position (j ev
/ \ +h
en r 0) which is propagated into the i— position by a continuous series of
nonzero bits between i and i + j. When j = 0, the carry into the i — position
is zero; however, there may be a stored carry in that position. The general
Boolean expression for k. is given below. Note that a^ is not included.
U2i
* * t \ *
k. = a. ., a, a. _ ^ a, , a. _a. _a. 1 a. » v • • ° ^ \ II a. Ja,
1 l+l i+2 i+2 i+1 i+2 1+3 i+k i+h \l
kki
' I
( n a, +k )(a^  p)
k=l
Since the adder relation, a, a, , = 0, must always be satisfied, the
terms in the general expression for k. are orthogonal. That is, if k. = 1, one
61
and only one of the AND terms on the right side of the equation has unit value.
*
The (a j ^ p) term deserves special attention . Since the adder relation may be
* , rd
broken between A and Q, ai jl = p = 1 may occur. A carry into the 4 3 — position
*
will arise if either or both of an and p have unit value. Another unit is
added to the kh — position if and only if p = 1. Hence, k> , = p.
The physical realization of the k. functions is in terms of generate
and propagate conditions as expressed below. For convenience, these functions
are chassisoriented and therefore span two base k positions in the first and
fifth levels.
FirstLevel Logic
Carry Generation: G, = a* . v p = kj. (As shown on DIO99)
Carry Propagation: P, . _\ . = a. _a. „a. n a.
(i3)i 13 12 ll 1
* *
Carry Generation: Q, . _\ . = a. 1 ^ a. _a. ~a„ _
(,i  3)i i i + i"3 i2 i2
where i = Uq and 1 < q < 11.
SecondLevel Logic
G 33^ :: G 3336 v P 3336 G 37^0 v P 3336 P 37^l^ y ? 33  3 6 F 31ho P klhk%
P 2132 " P 212^ P 2528 P 2932
G 2132 : G 212U " P 212U G 2528 V P 212^ P 2528 G 2932
P  P P P
920 ' 912 1316 1720
G 920 G 912 v P 9l2 G l3i6 v P 9l2 P l3i6 G l720
62
ThirdLevel Logic
G 2lU5 ;: G 2132 s ' P 2l32 G 33^5
G Ql+5 = G ^ P G ^ P P G ,
920 920 2132 920 2132 33U5
FourthLevel Logic
G kik5 = G Uli+U v *kikk G k5
G 3T^5 = G 3T^0 v P 37^0 G Ull+U ^ p 3T Uo P l+l^ G l+5
G 29U5 = G 2932 v P 2932 G 33^5
G 25U5 = G 2528 v P 2528 G 2932 v P 2528 P 2932 G 33U5
G l7U5 = G i720 v P lT20 G 2lU5
G i = G / v p ,Q sy p .p G i
13^5 1316 1316 1720 1316 1720 21^5
G 5^5 = G 58 v P 58 G 9^5
G lA 5 = G l* v P lA G 58 v P lU P 58 G 9U 5
FifthLevel Logic
The following set of carry generate signals have "been formed in the
gt nd_ x'd. "tli
1 — , 2 — , 3 — , and h— levels . K. = G/ . \ . ^ where i = kq and < q < 11 « To
th
obtain the carry into the i — ■ position, k. , where i = kq_ and < q < 10, we form
_■*
k = a.K. and k, , = p
ill kk ^
Likewise, to obtain the carry into the (i  2) — position, k. , where i  kq_
\ and 1 < q < 11, we form
■63
k. = a. ,a.K.
i2 ll 1 i
The significance of these expressions becomes apparent if we exam
ine two special cases of the general carry equation. We know that k. and k,
may be expressed as follows:
\ 2 = %3%k {& lk v p)
The implicit outputs, k, _ and k, , can be written in terms of K, and K, i*e
%q ^ A k2
kO auu %2
spectively.
ho = %oho = a 4o (G UlW v P 4lWV
k U = a J *V) v a Ul a U2 a U2 v a UA2 a ^3 a ^ (a ^ V P)
_*
Since a^a^ = 0, we have a^a^, = a^. It follows that
a Hl a U2 a U2 v \i a U2 a U3 a UU (a l+U
k],o = : a n ,a )i0 a )i0 s< a,,, a lin a )l0 a )l)l (ai 1 , 1 ~ p)
In terms of K, we have
k U2 = a U3 a i^V = %3%h% = % 3 %k(%k v p)
_*
It is easy to generalize these arguments to show that k. = a.K. or
ill
k. _ = a. , a.K. for all even i in the range < i < k2.
i2 ll 11 °  
t
The KgA gate and b. signals are also introduced in the fifth level,
The principal outputs of the carry generator are expressed as follows:
b. = b. v k.(KgA)
l l l
■6k
\2  b i2 V \JW)
where k. and k. _ are defined above. Because of the action of the MsA selector,
1 12
t
b. = when KgA =1, so b. = k. when KgA = 1.
The outputs K and k are used in the sign A logic and high A bit
path logic respectively. The K n = G . signal is formed as indicated above,
while the k , signal is generated as
k i = ( a K o )KgA
The choice of k as a symbol to represent this signal is unfortunate since
in general K. = G, . \ , for i even. Note that when KgA = 1, k , represents
the carry into the (l) position.
3°1°9 The a Logic
As shown on the right side of the DPa drawing (D1507); the OL logic
is fed by the a , OL , OL } OL a and a. outputs of the A adder. Its outputs are
i
Ctov, Onz, nCK, and no: with their complements. These outputs are distributed to
the various control sequence steps as indicated. It is important to note that
these outputs are meaningful if and only if KgA = 1 and sufficient time has
elapsed to permit the carry generator and A adder to react. Under these condi
tions, the A adder output, OL } represents the assimilated value of A with or with
out roundoff o The Boolean expressions for the four outputs are given below.
ccov = a a s/ a _i a o
If Ctov = 1, a is overflowed Mod 2, i.e., OL ^ a
anz = [(a^a )(a_a^)]
.65
If Cttiz = 1, a is nonzero since at least one of the outputs a , a .
OL , a , and a, has unit value.
na = [oL OL ± a 2 v OL Q a^x 2 )
7 117
If na = 1, I7< Q;< "I7orr<a<r. If aov = when na = 1,
then l<a<rorr<a<l which corresponds to the normalized range of OL
except that OL = is not included. Therefore, even though na is associated
with the normalized a condition, it does not always imply this condition.
na = a a x a 2 (a 3 ^ a^) v a^a^a ^ a^)
If na = 1, then a lies within one of the following ranges
§<«<§ *<<&
1 ^ ^ 1 28 ^ ^ 31
JE^ a< h lS^ a< S
• 1111
If Otov = when na = 1, then  r < OL <  ry or TZ S. a < 77* Therefore, the
condition (aov)(na ) = 1 implies that a will be normalized after one base h
shift to the left.
In many cases when na and na are sampled, it is known apriori that
a is not overflowed. This is true in both the normalized (r) and shift (f) se
quences as a consequence of leaving the accumulator in a nonoverflowed state
at the end of every Delayed Control instruction. Note that aov is not used
in either the \RJ or \FJ sequences. In the store (s) sequence, aov appears in
conjunction with na because roundoff may cause overflow. These considerations
are also discussed in the sections which deal with the (jy , Cly> and [SJ control
sequences.
66
3 . 1 . 10 The A, S, M and R Normalization Logic
These individual blocks of logic are shown on the upper half of the
SEC drawing (D1527). The Boolean expression for each is given below.
na = a a a v a„a, a_
12 12
ns = s oSl s 2  s oSl s 2
mn = m m m v m m m
nr = r r r ^ r r r
12 12
If any of these expressions has unit value , the contents of the corresponding
7 117
register must be in the range  r < f <  y or y < f < y. If it is also known
that the register does not hold a number which is overflowed Mod 2, then f must
be in the normalized range: 1 < f <  y or y < f < 1.
The na and ns outputs are valid only when the stored carries in the
A and S registers are assimilated.. These signals and their complements are used
in the shift ( S) sequence exclusively <> Because the accumulator is left in a
nonoverflowed state at the end of every Delayed Control instruction, the con
dition that na = 1 or ns = 1 implies that the number contained in the A or S
register is in the normalized range.
The nm and nr signals and their complements are used only in the
division (in sequence. (See section 5° 13°)
The DIV and NDV orders place the divisor in M as the initial operand.
Therefore, it cannot be overflowed in the fractional part. It follows that if
mn = 1, the divisor is normalized. The VID order obtains a divisor by normal
izing the accumulator and then rounding. As a result, the fractional part of
the divisor which is placed in M is either zero or in the range r < f  < 1.
6 T 
Thus M may contain a f =  r or +1. If f =  j, nr = 0; while if f = +1,
run = 1 since f looks like 1 to the mn logic. This situation does not cause
trouble in the VID because the x signal masks nm at the D2 control point. (See
DC Flow Chart D1128.)
For any divide order the nr signal is used to determine when a "nor
malized" quotient has been formed. The condition nr = 1 causes an exit from the
iterative loop (control points D10 and Dll). At the time of exit, R may or may
not contain an assimilated representation of the ■unrounded quotient. There may
be an effective stored carry in the "R^ n " position which would be absorbed as
soon as a negative quotient digit (bits i\ p > Pho> an ^ P),), ) is generated and
%k
ed in R f G , R, , and Rj . The "R, " memory element does not exist; but if
l k2> "43 j
44
40
it did, it would contain a carry bit under certain conditions during the gen
eration of a quotient. If "Rj, n " contains a carry and a nonzero negative quo
tient digit does not arise before the division terminates, the carry remains
and must be assimilated to obtain the true representation of the unrounded
quotient, (A detailed explanation of quotient generation is given in sections
3.1.17 and 5°13°) The point of interest here is the fact that the bit pattern
in R , R and R may change if the effective carry in "R, " were assimilated.
0' 1
40
This change would also cause nr to change in the cases shown below,
R Bit Po
sition
P. = 
1
4~ '■
R = +1
1
0.
1
2
3
4
1
1.
1
1
1
0.
1
1
0.
1
1
1
1
1.
1.
1.
39
40
"40 "
41
42
42
^3
1
1
1
1
1
1
1
1
1
1
1
1
44
R, contains a stored borrow in these cases, but it must be ignored since both
Ri _ and R, , contain zeros, which means the last quotient digit generated was a
negative zero.
68
In the first and third cases, nr = 1, but the unrounded quotient is not
normalized since R =  r or +1. In the second case nr = 0, but the unrounded
quotient is in fact normalized, since R  + — . Since nr = another pass through
the divide loop occurs. If a negative quotient digit is not inserted during
this pass, case 3 will arise. None of these cases causes any difficulty, since
 r and +1 are both valid unrounded quotients. The effect of rounding is con
sidered in section 5«13« I n all other cases, nr gives a true indication of
whether or not the unrounded quotient is normalized.
3.111 Sign A and Sign Comparison Logic
This logic is shown in the upper right corner of SEC (D1527). As
its name implies, it is used to obtain the true sign of A and to compare that
sign with the sign of M. Since the K output of the carry generator is used,
the MsA selector does not have to be set to KgA to obtain the true sign of A,
This is of no consequence as far as the use of the Sign A signal is concerned;
however, it is a necessary requirement for generating the sign comparison sig
nal, 7, during the divide loop.
Sign A =
a_l © a K Q
= a l a o K o
The true sign of A is always taken as the assimilated value of a ,
Since a n K represents the carry into the A position under assimilation (see
section 3>l8)> Sign A can be expressed as shown above.
7 = (Sign A)m ^ (Sign A) m
The sign of M is always determined by the contents of M , . If A and
M have like signs, 7=1. Since the sign comparison signal, 7, is used only
during division, the signs of the partial remainder in A and the divisor in M
69
agree if 7 = 1 and disagree otherwise. An explanation of the use of 7 is given
in sections 3»1°17 and 5»13»
3 . 1 . 12 The Q and R Half Subtracters
The Q and R halfsubtractor logic is shown in the lower left corner
of SEC (D1527). These halfsubtractors are used only in case 3 of floating
addition. In this case, the exponent of the augend (subtrahend) is larger
than the exponent of the addend (minuend) so the fractional portion of the aug
end (subtrahend), AQ, must be circularly left shifted until the exponents agree.
The accumulator is assimilated during the first transfer from A to S in this
shift process. This places the most significant bits of the augend (subtrahend)
in the least significant portion of the Q or R register at the time addition
i subtraction) occurs.
As a consequence of this addition (subtraction), a borrow or carry
or neither may be generated in the (l) position. If a borrow is generated,
the Q and R halfsubtractors are used to propagate it into the most significant
bits of the sum (difference) during the circular right shift into AQ, The Q, i
and Ri , memory elements alternately hold the borrow during propagation. If a
carry arises, the high A and S special adders (section 3°1°^) propagate it into
the most significant bits of the sum (difference) during the circular right
shift into AQ. A and S alternately hold this carry during propagation.
Whenever a borrow is not generated at the time of addition ( subtrac
' ' ' '
tionj, the oc , QL and a o> o_ P outputs of the Q and R halfsubtractors are
simply copies of %?> %], and \n> r kk> anc ^" ^ e Qkk and R, 1 memory elements are
always set to zero. In any case the a. and a ( a ^ and o P ) outputs of the
Q (R) halfsubtractor are used to set S and S (A and A ) during the circu
lar right shift. (See sections 3.1.2.8 and 3.1.2.6 for bit path details.)
•TO
Q Half Subtrac tor Logic
#
ma = q, ^(OMsA) v a^b (OMsA)
a
3 = ^3 © (% h )(*a_ 2 )  ^1+3 ® C3 U^ (n °2 )
a _2 " V © ma _ 2 = V ® ma 
R* u = (cr) (q^)(q ul+ )(i^_ 2 )
R HalfSubtractor Logic
*
m
a_ 2 = r uu (OMsS) v s_ 1 t_ 1 (OMsS)
°3 = r l^ 3 © ( r ^l + )(ma 2 ) = r U3® (r © (ma ©
a o = r
© m °_ 2 = r UU© mCT 
V = ( cr )( r U 3 )( r ^)( m a_ 2 )
These expressions are best understood by analyzing a case 3 addition
(subtraction) in the (l) column. Assume that at the end of the circular left
shift, the most significant bits of the augend (subtrahend) lie in the least
significant bits of the q(r). The addend (minuend) in M is added (subtracted)
to that portion of the augend (subtrahend) that is in A(s). The result is cir
cularly right shifted one base k position into SR (AQ). This is generally only
the first of many circular right shifts. At the time of addition (subtraction),
71
the augend (subtrahend) is always assimilated in A(s) because KgA = 1 during
the first circular left shift. (This is clearly necessary since Q and R cannot
hold stored carries.,) The a , (s ) "bit has positive weight in this case. The
b , (t , ) bit has negative weight as usual. Let c (x ) be the carry into the
a (s ) position. Let OL (a ) and a (a p ) be the sum and stored carry bits
as usual. Let (3 (t p ) represent the borrow from the 2 position. Expressions
for Q£_ 1 (a_ 1 )> a _2^ a .o^ > and ^2^ T 2^ in terms of a _i^ s _i^ ^l^i^ and
c (x ) can be derived from the truth table shown below. Keep in mind that
a _(a P ) are formed as in any standard base k pseudo adder. (See sections
3.1.3 and 3.I.U.)
Weights:
+2
2
+2
+2
+k
Variables:
a_ x (s_
1
1
1
1
.1)
b
A
1
1
1
1
1)
c_ 1 (x_
1
1
1
1
.i>
a
.A
1
1
1
1
.1)
* 1 * \
1
1
1
1
a _l = a _l © b _ x © c _ x
CT 1 = s l ® t l ® x l
a l = ( a _l © b _l) c ._l
°2 = ^ S l ® t l' )x l
P2 " a l b l
T 2 " 'l*!
Note that the equations for a ( a ) and a ( a p ) agree with those given in sec
tion ^.l,k.
During the first circular right shift into SR (AQ) the MsA (MsS) selecto:
■7
P
is set to MsA ( MsS) or MsA (MsS) while the MsS (MsA) selector is set to
OMsS (OMsA) . On the second circular right shift, MsA (MsS) is set to OMsA
(OMsS) . Thus, if
%3
= q
kk
= o (
h3
r, . = 0) during the first circular right
shift into SR (aq), the borrow is propagated and must be stored in R, > ^kk^*
# x
If r^ = ? ]+k =0 and R^ ,■ 1 (q^ = q^ = and Q^ = l) during the second cir
cular right shift into AQ (SR), then the borrow is again propagated and must be
■x x
stored in Q^ ( R i^) *
It follows that a unit no p (ma p ), must be subtracted from
%y \k ( r ky r k0 if P 2 = ! ( T _ 2 = X ^ and 0MsA = 1 (° MsS = ^ or
x x
q, , = 1 (r, , = l) and OMsA = 1 (OMsS = l). The corresponding Boolean expres
sions for ma and ma p were given above where (3 = a b and t = s t .
Note that a ,b
_ ± (OMsA) (s_ 1 t_ 1 (0MsS)J
determines no ( m a Q ) on the first
2
circular right shift into SR (AQ); and that q, , (OMsA) ( r , , (OMsS)) determines
no p ( m G p ) on every odd circular right shift after the first. The equations
for the half subtractor logic can be derived from the following truth table.
c lk3 (r k3 ) q kk (r W ^_ 2 ( m a_ 2 )
1
1
1
1
°L 3 < a„ 3 )
1
1
1
1
a _ 2 ( a 
■2>
vKk)
1
1
1
1
1
The cr signal, i.e., the true output of the CR status memory element,
is included in the expression for setting R, 1 and Q, . in order to clear these
memory elements to zero when they are not in use. The CR memory element is
turned on (i.e., set to "l") at the beginning of a circular right shift and
•73
when the shift, is completed.. The circular left and right shift
•*
facility is used only during case 3 of floating addition Therefore, R, >
*
and Q) , are always set to zero except when a borrow is being propagated dur
ing a circular right shift following a case 3 addition, (See section 5°1°)
3.1.13 The CarryBorrow Logic
This logic appears in the lower right corner of SEC (D1527). In
case u of addition, it is used to detect and temporarily hold a carry or
borrow into the most significant half of the sum or difference. In division,
It is used to detect and hold the result of a sign comparison between the di
visor and the final partial remainder. (The final partial remainder is not
the same as the remainder which is left in R at the end of any division. For
details see section 5»13»)
The input to the CB memory element will be called CB even though it
is not shown as such on the logic , As usual, the output of CB is called cb.
In the following equation o is the true output of the A p status memory ele
ment. A~ is set to "1" during the first pass through control point D10 in di
vide. Its true output, S , affects the carryborrow logic as shown below dur
ing D12, ana the resulting output is gated into CB during D13. (See Delayed
Control Flow Chart.) During Dl^, A is set to "0" such that 6=0, A^ is
true (& = O) during all other control sequences including addition.
CB = a_ 1 m_ 1 (m v & 2 ) ^ Q!_ 1 m_ 1 (m v & 2 )
The significance of this logic will be discussed first in relation to
case h floating addition. In this case, the CB output is gated into CB during
All. (See the DC Flow Chart D1128.) If cb = 1 after this gating operation,
is interpreted by the conditional logic in A12 as either a carry or borrow
_ T U
depending on the sign of M. If cb  0, it is interpreted as neither a carry
or a borrow, and A12 causes nothing to be added to the least significant bit
of the most significant half of the sum.
The carryborrow logic was suggested by R. H. Farrell. To understand
its function in case k addition, it is necessary to look at the way this par
ticular case of addition is executed. In case h addition, the exponent of the
augend (subtrahend) is so much greater than the exponent of the addend (min
uend) that the latter must be added (subtracted) to the least significant part
of the former. To accomplish this, the most significant half of the augend (sub
trahend) is placed in Q, and the least significant half is placed in R with
zeros in S, (See the DC Flow Chart and section 5.5.) The addend (minuend) in
M is then added (subtracted) to the zeros in S and the result gated straight
down (without any base k shift) into A, As a consequence, the contents of A
are then always added to the least significant half of the augend (subtrahend)
which is gated from R to M during A7. Prior to the addition, it may be neces
sary to shift the contents of A right until its original exponent difference
has been reduced to zero. The addition of M therefore may be to either A or S.
At the time of addition, the quantity in A or S is signed and may lie
anywhere in the range: 1 < f < +1. Note that +1 must be included because the
minuend may have been 1. The quantity in M is always positive or zero and may
lie anywhere in the range: < m < k. The point in M is taken between M and
M as usual, Both M and M have positive weight since they were originally
Q_, and Q, j i.e., the ^5 — and k6 — bits of the augend (subtrahend). The sum
A + M or S + M is always placed in A during the A10 control step prior to leav
ing the add loop (A9A10). The limits on the quantities added insure that the
sum in A lies in the range: 1 < f < 5. It is clear that a carry must be prop
agated into the most significant portion of the augend (subtrahend) if ^ < f < 5.
Likewise, it is clear that a borrow must be propagated if 1 < f < 0.
75
It is possible to establish whether the sum lies in either of these
ranges by examining the sign of the sum and the range of M, To determine the
sign of the sum which is in A, we make use of the fact that the MsA selector
is set to KgA during A10 in the final pass through the add loop (A9A10). This
means that the assimilated value of A appears at the output of the A adder, a,
as control passes to All, The true sign of A, i.e., the sum, is given by (X
at that time. If a = 0, the sura, a, must lie in one of the following ranges;
CCt<2orU<Q!<5° We determine which range by knowing the range of M, In
order for the sum to lie in the higher range, it is necessary for 3 < m < k
Note that it is never possible for the sum to lie in the lower range when
3 < m < K„ Thus, if Ct m m = 1, a carry must be propagated into the most sig
nificant part of the augend (subtrahend) which then becomes the most signifi
cant part of the sum.
If a = 1, the sum, Ct, must lie in one of the following ranges:
1 < 2 < or 2 < a < H, As before, we determine which range applies by know
ing the range of M. In order for the sum to be in the lower range, M must be
in the range < m < 1. Furthermore, if m is in this range, the sum cannot lie
in the higher range. Therefore is <xm,m = 1, a borrow must be propagated in
to the most significant part of the augend (subtrahend) which then becomes the
most significant part of the sum.
We note that a carry or borrow must be propagated if
(X ,m m ^ a. m m has unit value. This expression is identical to the
expression for CB when 6^ = 0, which is always true except during division.
Even though CB is stored in the CB memeory element in All, it is still
necessary to decide whether cb = 1 is a carry or a borrow. This is done by the
conditional logic at the A12 control point. As shown on the Delayed Control
Flow Chart, the MsS selector is set to CS if (cb)m = 1; to MMsS if (cb)m = 1;
and left at OMsS if cb = 1 , From the above analysis, it is clear that cb = 1
only when m = m „ Furthermore, cb = 1 must be interpreted as a carry if
76
m = 1 and as a borrow if m  0. If cb = 0, neither a carry nor a borrow is
propagated. It follows that a carry must be added in the hk — position by
setting CS if (cb)m = 1; and a borrow must be added in that position by add
ing a field of units to S via MMsS, if (cb)m = 1.
In division, the carryborrow logic compares the signs of the di
visor and the final partial remainder as described earlier. The result of this
comparison, CB, is stored in the CB memory element during D13. The cb signal
is used in the conditional logic of T)lh where the remainder is corrected for
quotient roundoff and in D17 where the quotient roundoff is actually performed.
We note that CB = OL , © m when 5 p = 1. As such, CB has opposite
parity with respect to the sign comparison output, J , that is used during the
divide loop (DIODll). (See section 3»1«H«) Because A changes, the 7 signal
could not be used in determining quotient roundoff unless it were stored in
some manner. Instead of storing 7, it was convenient to convert the carryborrow
logic to sign comparison logic using 6 and then store the output as in addi
tion.
The final partial remainder is placed in A during D12. (See the DC
Flow Chart, D1128. ) During this same control step, the MsA selector is set to
KgA such that the A adder output, a, represents the assimilated value of A after
sufficient time has been allowed for the carry generator and adder logic to
react. The true sign of the final partial remainder in A is thus given by Ct .
(The partial remainders in A always lie in the range: 2. < s. < —. See section
3.1.16.) The divisor, d, may lie in either of the following ranges:
1 1
l<d<,orr<d<+l. A divisor of +1 may arise while executing VID.
hk
If the accumulator equals 12 after normalization, then roundoff on the
way to R during D2 may yield a +1 divisor. Therefore, the true sign of the
divisor in M is given by m in all cases.
If a , / m , a unit is stored in CB. The significance of the cb
77
signal in determining the quotient roundoff and the prior correction of the
remainder is discussed in section U.13.
3 . 1 . lU The Decoder
Although in a strict sense, the decoders are not a part of the
MAU logic, they are considered here for convenience and because they are the
simplest of the decoders which set the MsA and MsS selector mechanisms. They
are used only in the add (a) and clear add (b) sequences. The logic is shown
on the right side of (J.8D (DI506). The outputs of the 9, and status memory
elements are decoded to form set signals for the MsS and MsA selectors as des
cribed below in negative logic,
0MsA Decoder Logic
MsA
 = (e v 9 ) v ©MsA
MsA
9 = (0 v ) v/ 0MsA
0MsS Decoder Logic
2MsS
 = (0 v ) v 0MsS
MsS
MsS
2MsS
 = (0 v ) v 0MsS
 = (0 v © 2 ) v 0MsS
= (0 v ) v 0MsS
The status memory elements are set during some control step, usual
ly decode (Gl), prior to the step that uses their outputs to set the MsA or MsS
selector mechanisms.
78
9 Outputs Operation
a
«
l
2
l
1
l
1
Subtract M
Add M
Subtract 2M
Add 2M
As indicated earlier, the requests from a control point are in the
form of zero (negative voltage) outputs. All selector mechanisms respond to
zero inputs. The 9 decoder logic, as well as the u. and P decoder logic described
below, must generate zero outputs in the active stage. For example, to set the
MsA selector to MsA, via the 9 decoder, it is necessary to make MsA 0=0.
This can only occur when 9 =9=0 and a control point request for 0MsA is
present, i.e., when 0MsA =0. As long as 0MsA = 1, the outputs of the £MsA de
coder have no effect on the MsA selector mechanism. (See section U.2.) Simi
lar statements can be made with regard to the 0MsS decoder.
3.1.15 The n Decoder
Most of this logic is shown in the left and center sections of I0D
(DI506). The remainder is shown as part of the input logic to Qi p and R. on
LQR (D152^). The principal outputs of the u. decoder set the MsA aid Ms S selec
tors during multiplication.
A brief description of the multiplication instruction is included at
this point to clarify the discussion of the u decoder logic. A detailed descrip
tion is given in section 5.12.
At the beginning of the multiply instruction, the multiplier is in
AQ and the multiplicand is in M. The normalization sequence Qu is used to
shift the multiplier left until it is normalized or Q = 0, whichever occurs
79
first o It is then rounded and transferred to R while zeros are placed in S.
The two least significant bits of the rounded multiplier, a. and a, > , are
recoded by the uMsS decoder logic on their way to Ri _ and R, i . The output of
this logic sets the MsS selector to one of the following: 2MsS, MsS, OMsS, or
\2
_ _ *
MsS. If MsS is set during this initial step, a unit is also gated into R, as
shown on LQR (D152U).
On the following step, the next two multiplier bits, r, and r, , and
the mode bit, r> , are recoded by the uMsA decoder logic. The output of this
logic is used to set the MsA selector to one of the following: 2MsA, MsA, OMsA,
or MsA. Another output on LQR is used to set Q, during the down right transfer
of S + l ; ' R into A,Q. After the transfer, As + iM,R) appears in A,Q. If
r,„ = 1, the r, and r, bits are modified by the borrow subtr actor logic (see
section ^.l.Yj) before they are gated into Q, _ and Qkk* This does not affect
the setting of the MsA selector. If 2r^, + r, p + r» p > 3> Q1.0 i s se "t "to 1 by
the uMsA decoder logic.
On the next step, q, , q> p and q> are recoded by the uMsS logic.
The outputs of this logic set R. p = 1 if 2q,  + q, + q. > 3, and set the
MsS selector to one of the four options listed above. During this step,
r{A + uM,Q) is placed in S,R. The q, and q, multiplier bits are transferred
to Ri „ and R, , without modification. Even if modification occurred during
transfer, it would not affect the multiplication.
This process continues until the two sign bits of the multiplier
have been sensed by the uMsS decoder logic in Qi and Q« . The up right trans
1/ \ *
fer places r(A + UM, QJ in S,R with R, set to 0. The following straight down
transfer places S + iM,R in A,Q as the double length product. Q, p = while
Qi and Q, , contain the sign bits of the multiplier at this point. By setting
k2
#
Ri = during the last transfer into R, the borrow subtr actor is prevented from
80
modifying the two least significant bits of the product, ri and r. , as they
are gated straight down into Q, , and Q^p
The multiplication algorithm is based on a recoded multiplier. The
recoding is accomplished by the u decoder logic. The primary reason for re
coding the multiplier is to avoid the need for 3M as a multiple of the multi
plicand. Such a multiple would be necessary if we simply examined two bits of
the multiplier at each step. In order to emphasize this point, the M selec
tor settings required in each case without recoding are listed below.
Multiplier
Bits
M
Selector Setting
OM
1
M
1
2M
1 1
3M
To achieve 3M, we could add 2M to A ( S) , shift straight into S ( A) ,
add M to S ( A) and shift right into A ( S) , As an alternative, we could create
a special adder between M and the M selector OR's such that 3M appears at its
outputs shortly after M is loaded. With this device, we could simply select
3M, add it to A ( S) , and rightshift the result into S (a) . Neither approach
is satisfactory, since the first is too slow and the second is too expensive.
A better solution is achieved by recoding the multiplier to take advantage of
the fact that addition and subtraction are equally easy to implement in the
two's complement system.
Let
hk
y = 2y + y + E y 2
1 ° k=l k
represent the rounded multiplier. Because of roundoff, y may have a value
81
of +1 so y is not always equal to y . In order to take advantage of the base
h shift between A,Q, and S,R, two bits of the multiplier are examined at each
step. Therefore, it is convenient to express y in terms of 23 base k digits ,
h'
22
y = P = B + Zp> _1
1=1
where
P = 1, 0, 1
and
B. = 1, 0, 1, 2
for
1 < i < 22
We require that B = B . This can be guaranteed if we relate B. to B. as
follows :
B. = B. + \.  h\. _
i i i iI
where
\. = 0, 1
i
for
1 < i < 21
with
•82
K ..
and
X 22 = °
The X. are called mode bits.
1
To prove that (3 = P if the P. are related to the p. as indicated
above, we consider p  p,
22 22
P  P = P + x Q + Z (p. + x  hx^K 1  p Q  £ p ir 1
1=1 1=1
22 . 22 , , _ x
= x n + Z xX x  Z \. u^" 1 ^
i=l i j=l J' 1
Let j = i + 1 in the second sum and remember that \ = 0,
, 21 . 21
6  p = x + Z x.U 1  Z x.iT 1
. l i
1=1 1=0
p  e  ^  \  o
The rule for choosing X. given P. and X. is stated below for
1 < i < 22,
X. n = 1 if 3 < P. + X. < h
iI — i i —
X. n = if < P. + X. < 2
iI  i l —
This is not the only rule that might be used to choose X. if 2M, M, 0M,
M, and 2M are available options for both the MsA and MsS selectors . The
choice of this rule was partially based on the M selector requirements of
83
the (Bj and (d) sequences. Since a binary division algorithm is employed, the
2MsA option is not needed. However, all five of the above options for the MsS
selector are used in the (b) sequence. By recoding the rounded multiplier
according to the rule given above, it is possible to eliminate the 2MsA option
entirely. Note that 1 < p. < 2 when the A., are chosen by this rule.
Positive
Mode
Negative
Mode
<
^
h
l
t
Selector Setting
\x
OM
1
1
M
2
2
2M
3
1
M
1
1
1
M
l
1
2
2M
2
1
1
M
1
3
1
OM
1
At the time of recoding, p. is located in R, R,_ or Q, , Q.
while the mode bit, V, is in R,_ or Q, .
The Boolean expressions for the uMsA decoder (D1506) can be de
rived from the above table. On the (22i) — step of the multiplication
process, let (3. = 2r, + r, and let \. = r, . Negative logic is used to set
the selector, since it responds to zero inputs. The signals M3  (J. Ms A,
M5  a and M5  b go to zero when the designated control points become ac
tive and thereby cause the [iMsA decoder outputs to set the MsA selector. Let
u 2 Aa = (M3  u 2 Ms)(M5  a) and u 2 Ab = (M3  i 2 MsA)(M5  b).
2MsA = (r Ul v r h2 sy r^ v u^b)^ v r^  r^  n g Ab)
MsA = (r Ul v r k2 v r U2 v/ UgAbXr^ v r^ v r^  ^Ab)
8U
# #
OMsA = (r Ul  r h2  r^  ^Aa)(r Ul  r^  r^  ^Aa)
_ * — *
MsA = (r U] _  r h2 v r^ v/ u^AaKr^  r^  r^  ^Aa)
The AND in these equations is actually formed at the input to the MsA se
lector logic shown on MsAI (DII76).
The positive logic used to set Qj_ is shown on LQR (DI52U). The
signal, [i, is the true output of the u. status memory element which is set
to "1" during Ml and reset to "0" during the last pass through M6. (See the
Delayed Control Flow Chart . )
%2 = r Ui r U2 V r lU r te
.At t 1 1
Note that Q = \. which is the mode bit associated with the (il) — base k
k2 * th
multiplier digit and the (22  i+l) — step of the multiplication.
Except for slight modifications, the logic shown above applies to the
uMsS decoder as well. The modifications consist of substituting q for r and
ANDing in another term to permit recoding the leastsignificant multiplier
digit as a is transferred into R following roundoff. Since the least
t 1
significant mode bit always equals zero, A. pp = 0, the values, of (3 and X
depend only on a> and a, , as indicated below. In order to abbreviate the re
quest signals, we let u S = M2  u MsS, \i Sb = (Mh  u. MsS)(M6  b) and
^Sc = (VlK  u 1 MsS)(M6  c)
^. #.
2MsS = {q. kl  q. h2 v q^ v ^Sb)^ <* q^  q^ ^ ^Sb)^  0^ ^ u Q S)
# %■
MsS = (q Ul  q_ h2 ^ q^ ^ p^ScKq^  q^  q^  U^SbKo^ ^ 0^ ~ U Q S)
.£ #
OMsS = (q Ul  ^ sy q ^ s, ^SbKq^  q^  q^  ^Sb)^  0^  n Q S)
*3
85
— *
Its output controls the inputs to Q )Q and R )i0 as indicated by the above equations
MsS = (q kl  q U2  q^  l^ScKq^  q^ ^ q U2  ^ScXo^  o^  n Q S)
As before, the AND in these equations is actually formed at the input to the MsS
selector logic shown on MsSI (DII78).
The positive logic used to set R,„ is shown on LQR (DI52U), Since
KgA = 1 as the rounded multiplier, en, is being transferred to R, it is used to
condition the setting of Ri p on the initial step. During the iterative loop of
multiplication (control points M5 and M6) KgA = 0, so R, is set according to
*
the contents of Q, .., Q, 2 , and Q, 2 „
R *2 = % ± % 2 (^) ^ % ± % 2 (K&)  (\ 3 a kk (K&)
It is important to note the role of the \x status memory element (D1299).
l 2 and R* 2
Q, and R, cannot be set to 1 by the multiplier recoding logic if n = 0, i,e,,
if (i is true, During the last pass through M6, the count in the EAU reaches 1
— *
and p. is set as indicated by the Delayed Control Flow Chart, This means that Rj_
is set to zero during the last right shift into S,R, The two sign bits of the
multiplier (the sign digit) are in Qh^Q^p ^ the start of this step. During the
step, they are recoded as a regular bit pair and the MsS selector is set accord
ingly. However, if R, 2 is set to "1" as a consequence of this recoding, trouble
arises on the following step, The borrowsubtractor subtracts a unit from
R) ,Ri if Ri 5 = 1. Thus, if Ri = 1, the two least significant bits of the
product which are in R, n ^R^ 9 at the end of M6 on the final pass would be reduced
by a unit during the straight transfer into Qk^Qko which occurs in M7, The
ne^d to set Ri = during the last pass through M6 is clear,
A comment is also in order regarding the way in which the "sign digit"
of the rounded multiplier is recoded. This digit is represented by the sign bits
of the rounded multiplier, O. and Oi , Since the multiplier is normalized or
nearly normalized prior to rounding, the bit pair, a a may be 11, 00, or 01,
but never 10, Furthermore, 01 can only arise when the rounded multiplier is
86
+1 = 01,00 ... 00. It follows that may be 1, 0, or +1. However, at the
time p is recoded, it is in Q, , Q^ p ^ and Q, may be or 1 if p = 1 or 0;
but Q, = if 3 = +1. The recoding takes place during the final pass through
M6, so P n determines the setting of the MsS selector.
A case analysis follows. It was stated earlier that \ = 0, so
i
p o = p o + V
If = 1, the Q, = Q, = 1. The uMsS decoder logic sees p as +3
* ' —
instead of 1. If \_ = Qi p = 0, P Q = 1 and \ , = 1. MsS is set, but \ ,,
which is placed in Rk p , is forced to zero because \x is set to "0" during this
• *
step. Consequently, B n = 1 as it should and \ = 0. If \ = Qi = 1,
i
(3 = as it should so OMsS is set. Since jt is set to "0", \ is again forced
to zero even though it would have unit value otherwise.
If P = 0, then Q, = Q. = 0. The uMsS decoder logic sees as a
zero and sets OMsS if \ = 0, and MsS if \ = 1. In both cases, \ , would be
a zero anyway so the setting of u to "0" is not essential.
If P n = +1, then Q, = and Q, = 1. Since this can only arise when
the rounded multiplier is +1, all previous multiplier digits must be zero. The
equations for R, and Q show that \ will always be zero in this case. In
fact, Ri = Q. = at every step of the multiplication. Therefore, the uMsS
decoder interprets (3 as +1 and sets MsS. Here again X. = 0, so the setting
of u to "0" is not essential.
3 . 1 . l6 The Division Predictors (p Decoders)
The pMsA and MsS division predictor logic is shown on DPa (D1507).
It is used only during division. The outputs of this logic serve two functions.
First, they set the MsA and MsS selector mechanisms so' that the appropriate
multiples of the divisor are subtracted from the shifted partial remainder at
each step of the binary division process. Secondly, they are fed to the
87
quotient digit recoder logic , shown at the top of DKx (D1507), which produces
the base k quotient digit that is inserted in Rj,p> ^hof anc ^ ^kli on every sec
ond step of the division process.
To provide a background for the discussion which follows, a brief
description of the division process is included at this point. A complete des
cription is given in section 513°
In the MAU a modified, binary nonrestoring division algorithm is
1 , 1 , l
ed to divide the subnormalized fractional dividend, rr < D  < r, the
"normalized" fractional divisor, j < d < 1. The recursive relationships are
given below The rules for selecting the quotient "bit" (y . or y = 1,
2j 2J+L
0, or l) are complicated due to the stored carry representation of partial re
mainders. Consequently, the discussion of pMsA and pMsS logic (i,e,, the
selection rules) is relegated to the latter half of this section,
S 2j + 1 " ^ (a 2j " y 2j d)
a 2j+2 = S 2j+1 " 2y 2j+l d
j = 0, 1, 2 ... 22 or 23
The number of steps in the division process is controlled to yield a "normal
ized" fractional quotient, r < q < 1.
a„ = the subnormalized fractional dividend, tt < D'  < r, in AQ with
j = 1.
d = the "normalized" fractional divisor, r < d < 1,
s = the (2j+l) — shifted partial remainder in SR.
a . = the (2j+2) — shifted partial remainder in AQ,
y = the quotient "bit" (y = 1, 0, or l) generated by the pMsA logic
^ J ^ J
during the straight transfer in AQ,
= the quotient "bit" (y = 1, 0, or l) generated by the p MsS logic
2J+1 ' 2j+l
during the left shift into SR,
88
In all three divide orders DIV, NDV, and VTD, the divisor and divid
end are normalized prior to the fractional division. This is accomplished by
the (jy sequence and the first four steps of the (d) sequence. During D5, the
exponent difference is calculated. If the dividend is nonzero, it is subnormal
lzed in D6, i.e., shifted right one base U position into S, R. This is done to
insure that the fractional quotient is always in the range: 1 < f < 1.
The modified, binary nonrestoring division process begins at this
point. During D7, the MsS selector is set to OMsS. The subnormalized divid
end is gated straight down into A, Q and the pMsA predictor logic, which examines
the most significant a outputs of the S adder, sets the MsA selector to MsA,
OMsA, or MsA.
During D9, the most significant half of the first partial remainder
is formed at the output of the A adder and shifted left into S. The least sig
nificant half of this partial remainder is in Q and is shifted left into S and
R as usual. Bits Q 1 and Q go into S, and S. , as indicated in section 3.1.2.8,
During this transfer, the pMsS predictor logic examines the most significant
bits of the a output and sets the MsS selector to 2MsS, OMsS, or 2MsS. At the
same time, the quotient "bit" recoder logic (section 3.1.17) recodes the zero
quotient "bit" that is associated with the OMsS setting during D7 and the quo
tient "bit" (y Q = 1, 0, l) that is associated with the pMsA setting during D9«,
The resulting base k quotient digit (l, 0, l) is gated into R« , R^j,
(.01, 00, 11) during D9„ R. is always set to zero at this point to prevent
the borrow subtrac tor (section 3. 1.17) from modifying the two least signifi
cant bits of the dividend which are placed in R. , and R, during D9, If
Rk 2 = 1 during the first pass through D10, the borrow subtr actor reduces this
bit configuration by a unit in the h2 — position.
After D9 is complete, the control passes to the iterative loop of
8 9 
After D9 is complete, the control passes to the iterative loop of
division which consists of control points D10 and Dll . In D10 the new partial
remainder which appears at the output of the S adder is gated straight into A,Q e
The pMsA predictor sets the MsA selector to MsA, OMsA, or MsA according to the
most significant bits of this partial remainder. The associated quotient 'bit"
(y = 1, 0, l) is stored in G p , H ; and the quotient digit that was predicted
and stored during D9 or Dll is transferred from G, ,H to G ,H . In Dll, the
new partial remainder which appears at the output of the A adder is shifted
left one base h position and gated into S,R. The pMsS predictor sets the MsS
selector to 2MsS, OMsS, or 2MsS according to the most significant bits of this
partial remainder. The corresponding quotient "bit" (y = 1, 0, l) is stored
in G,,H . The quotient "bits" that were predicted on the two previous steps
are held in G, ,H. and G p ,H during Dll. The quotient bit recoder examines
the output of these memory elements and produces a base h quotient digit in
the range of 3 to +3 which is inserted in Rj, P > ^ho) an ^ Rj,k during this control
step.
is process is repeated until the count in the EAU becomes negative
Heating that 23 base k quotient digits have been generated) and the gener
ated quotient appears normalized in R. If the latter condition is not met, 2h
base k quotient digits are generated. (See the description of the R normaliza
tion detector in section 3* 1.10.) When the quotient appears normalized in R,
control passes to D12 where the final partial remainder and quotient are gated
straight into A and Q respectively and the MsA selector is set to KgA. The
al steps of the (jD) sequence round the quotient, generate a true remainder,
and compute the associated exponents.
Having briefly described the function of the division predictors,
we proceed to define their logic. Note that negative logic is used to set
■90
bhe selectors as usual. For example, MsA  p must be zero to
lector to MsA.
pMsA Predictor Logic
f s
m_ 1 (sa_ 2 ) v m (so )
m_ 1 (so_ 2 ) v m_ 1 (so_ 2 )
10
J
The signals so and sa
are outputs of the high
S special adder as dis
cussed in section 3.1.^.
* *
^2 = °2 °l " °2 °0 V °2 °0
MsA  p = £ 2 T1 2 v ^T^ s, QMsA  p
MsA  p = £ t^ v £ T} s/ OMsA  p
OMsA  p = o ^ o ^ a ^ a pMsA
OMsA  p = o o a a ^ pMsA
pMsA = (DT  Pl MsA)(D10  a)
In order for the pMsA predictor logic to set the MsA selector, pMsA
must go to zero as the result of a request from control point D7 or D10. (See
section h.2.) In the absence of such requests, the outputs have unit value
and therefore do not affect the MsA selector.
The G and H Eccles Jordan memory elements are used to hold the pre
dicted quotient "bit" which is interpreted as +1, 0, or 1. If
MsA  p = 0, then the divisor is added to the partial remainder on the next
step and the corresponding quotient "bit is 1, If MsA  p = 0,
91
then the divisor is subtracted from the partial remainder and the correspond
ing quotient "bit" is +1. If MsA  p = 0, the corresponding quotient "bit"
is zero. A zero input on the 1 or side of an Eccles Jordan causes the out
put on that side to assume unit value. The significance of the true outputs
of G and H in terms of the quotient "bit" stored is summarized below.
Quotient "Bit" Stored = y
(,j = 0, 1, 2 —  22 or 23)
+1
1
Let the 1 and side inputs to G~ and H be designated as Q ,0
2
h
1
1
1
1
1
and H H respectively.
G = (MsA  p)(0MsA  p) G = MsA  p
H 2 = OMsA  p H 2 = OMsA  p
The AND at the input to G^ insures that g = 1 whenever OMsA  p = 0.
pMsS Predictor Logic
h  ^i v *!<*_!
*! = m i a i v m i a l
\ = a a V ^1^2
\ " 5 v ^1 V ^ a 2 V a a 2
la
 P = S Tl v 5~ T]
"l'l l'l
2MsS  P n Lll, v ! n v OMsS  P
2MsS  P = I tj v  T) v OMsS  P
OMsS  p = a ^ a ^ a ^ a ^ PMsS
OMsS  p = a a a a v pmsS
PMsS = (D9  p MsS)(Dll  a)
The PMsS signal must go to zero as the result of a request from D9
or Dll in order for the PMsS logic to set the MsS selector. As long as PMsS = 1,
the outputs of the PMsS predictor have unit value and therefore do not affect
the MsS selector.
i t
The G, and H EcclesJordan memory elements are set as follows:
G = (2MsS  p)(OMsS  p) G^ = 2MsS  p
H = (OMsS  p)(gH ) H = OMsS  p
t i
The gH signal goes to zero during D6 to insure that h = 1 at the time H is
set in D7. As a result, h = 1 when the quotient "bit" recoder produces the
initial hase h quotient digit during D9. (See section 3. LIT.)
Quotient "Bit" Stored = y^ . _
2j+l
(,1 = 0, 1, 2  22 or 23)
+1
1
I
1
i
p
l
p
l
1
93
During D7, p = or 1 depending on how g was left at the end of the previous
divide order. During any pass through D10 in which h = 1, p = 1 because of
i
the AND at the input to G, .
i t
The logic for gating the contents of G, ,H into G ,H is given below,
G = g, ^ pMsA G, = g , ^ pMsA
H = h v pMsA H = h. v pMsA
The quotient "bit" (y = 1, 0, l) that is predicted during the
present pass through D9 or Dll is not used in forming the base k quotient digit
that is inserted in R^o, ^Lv an< ^ ^LL ( ^ ur i n S this pass. Instead, it is held in
t i
G ,H and transferred to G ,H during D10. In D7 or D10 the quotient "bit"
(y = 1, 0, l) predicted by the pMsA logic is stored in G ,H . During the
following pass through D9 or Dll the two quotient "bits" stored in G, , H , G
and H_ are recoded as a base 4 quotient digit which is inserted in Rk q , B., and
Ri i . Note that y always has twice the weight of y . . The quotient bit re
44 2j+l dj
coder is described in the next section.
Zero quotient "bits" arise as a consequence of the stored carry re
presentation of partial remainders. The true sign of fraction, f, in stored
carry representation is not always determined by its leading bits. If the num
ber of leading bits that one is willing to examine is fixed, there is a range
of f, t < f : u, for which these bits may or may not determine the true sign.
f is outisde this range, the true sign is always determined by these bits.
The number of leading bits that must be examined increases as t and u approach
zero. If the unshifted partial remainder, f, appearing at the output of the A
or S adders is sufficiently large, its true sign can be determined by the asso
ciated predictor. If this sign agrees (disagrees) with the sign of the divisor,
■94
m ., the divisor or twice the divisor is subtracted from (added to) the shifted
partial remainder on the next step; and a positive (negative) quotient "bit" is
generated. If t < f < u, the predictor may or may not be able to determine the
true sign. Consequently, the sign comparison may be incorrect. In this case,
zero is subtracted from (added to) the shifted partial remainder, giving rise
to a zero quotient "bit".
The last half of this section is devoted to a study of the underlying
basis of the pMsA and pMsS logic. The recursive relations are used to determine
the limits on the partial quotients and partial remainders. Knowledge of the
latter is fundamental to understanding the design of the pMsA and pMsS logic.
Dividing the recursive relations by d, we obtain the following expres
sions for successive partial quotients:
^2j+l d ^2j ^2j
q _. _2j+2 _ _
^2j+2 d ^2j+l ,y 2j+l
where y and y = 1, 0, or 1 and j = 0, 1, 2 22 or 23.
To find the steadystate positive limits on the partial quotients,
let y 2J = y 2J+1 = land let (Q 2 j +2 ) MeDC = ( Q 2 jWx' Substltutin S the second ex
pression into the first, we obtain
^2J + lW ■ ^W«ta  2]  k
It follovs that (Q 2J+1 ) Max = k and (Q 2J+2 ) Max = 2.
The steadystate negative limits are obtained in the same way with
y 2j = y 2j + l =  1 md ^2j + 2 } Min = (Q 2jW
■95
'WMln = ^'V'ltn +2]+k
Therefore, (Q_. _ ),,. = h and (Q . _)... = 2.
' 2j+l Mm 2j+2 Mm
Figures h and 5 provide a graphic picture of the generation of suc
cessive partial quotients. The partial quotients have no particular signifi
cance except that they are not a function of d, and therefore Figs, h and 5 are
valid for all d, y < d < 1, Furthermore, the limits on the partial remainders
can be easily derived from the limits on the partial quotients.
y
2j
y 2j " +1
Figure h. Q 2 . + 1 = h^.  k 7
■ 9 6
= 1
w
Figure 5 . Q 2  +2 = Q 2J+1
2y,
j+i
In Fig. h, note that y =0 is not allowed unless 1 < Q < 1.
Likewise, in Fig. 5, y _ . . =0 is not allowed unless 2 < Q~ . , < 2. These
' ' 2j+l  2j+l 
limits may be translated into limits on the unshifted partial remainders o
2j
and a . Using the expressions for Q . and Q_ . , the limits on Q imply
^.1+L 2,1+2 2.1' 2,1
2j'
"2j
 d ... < a . < Idl... , and the limits on Q A . . imply 2 Idl... < s_. . < 2d... .
1 'Mm  2j  ' 'Mm' 2j+l ^ J ' 'Mm  2j+l  ' 'Mm
The limits on d are r < d < 1 where both  r and +1 may arise as the result
of roundoff in a VID order. (See section 5.13.) Since cu • = a o • and
2j 2j
Q * "l "l 1
= — r — , On must lie in the range   < 0n i S 17 before y Q ^ = is al
o.
2j+l
h  a 2j  h
2j
lowed, and Q^ . . must lie in the range  o < QL . , < q before y^ . . = is
' 2j+l B 8  2j+l  o 2j+l
allowed.
The outer limits on the unshifted partial remainders Oo . and a .
* u 2j 2j+l
are determined in a similar manner. Since 2 < Q_ . < 2, 2 dL. < a . < 2 1 d
 2 j  ' ' 'Max  2j  '
which implies 2 < CT _ . < 2. Likewise, U < Q_ . , < h implies 1 < a_. . < 1.
 u 2j  '  2j+l  *  2j+l 
We are now in a position to consider the number of leading bits of
'Max
Ob* and a that the pMsA and pMsS logic must examine to predict the appropriate
J 2i
2J+1
•97
quotient "bit". There are two problems here. First, we determine the number
of "bits" to the right of the point that are necessary to insure that o . or
OL is within the prescribed limits when a zero quotient "bit" is predicted.
Secondly, we decide how many "bits" to the left of the point are needed to de
termine accurately the sign when the unshifted partial remainders assume their
maximum values.
To insure that the true sign of a is known whenever a <  r or a > y,
so , a , a , o n , and a are examined. The basis for this assertion is dis
cussed later. The apparent sign of a is so p © ^p. ^\ is the apparent carry
into the 2 position, and is defined by one of the equations of the pMsA logic,
If sa_p © ^p = Q> cr must be positive since any stored carries to the right of
a have positive weight. If s a p © T] = 1, is apparently negative but may,
in fact, be positive due to stored carries to the right of cr n . Therefore, the
negative inner limit, CT =  r, determines the number of leading bits of c
which must be examined to insure that a zero quotient "bit" is predicted if
and only if  j < < r.
Assuming the divide control sequence is functioning properly,
a 1 ajO, a p = 1 implies that sg = 1. If s<j p = under this condition,
would be greater than +2 which is outside the limits of the division process
as discussed above. Furthermore, a o^o^ a P = 1 together with the adder rela
tion guarantees that a  o n  0. Consequently, if a = 1, the true sign of
a is positive while the apparent sign is negative. This also applies for
any stored carry to the right of q , provided that there is a string of units
between it and a . The condition o , o n o, o = 1 also guarantees that
 r < a <; To The positive limit is the sum of the infinite stored carry re
presentation shown below,
98
111 1
1 1 1 1.1 1 1 1...0 1...
*
If o Gr) * a o = 0, a stored carry in the a position or to the right of
the a_ position cannot propagate into the 2 position and affect the sign of o.
The apparent sign must therefore agree with the true sign. Note that
o a o.a = does not imply that a <  r or r < a. Thus, there are stored car
ry representations of O. in the range  r > a < y for which the apparent sign must
agree with the true sign.
The function of the pMsA logic is summarized as follows. The appar
ent carry into the 2 position is tj = o v a a o The apparent sign of a,
so Q r\ , is compared with the true sign of the divisor, m . In negative log
ic, this comparison is defined by MsA  p = £ r\ where L = m @ so . This
comparison is meaningful if and only if the apparent sign of a and its true sign
agree. If o o o o = 0, this agreement is guaranteed, so MsA is selected if
MsA  p = (i.e., if the signs of the dividend and divisor agree), and MsA is
selected if MsA  p = (i.e., if the signs of the dividend and divisor dis
agree). If a o o o = 1, the apparent sign of a may not agree with the true
sign of a, so OMsA is selected. This selection does not cause the division
process to go out of bounds in S (i.e., s„ . . = ka. . n within Uldl : s_. n < Uldl)
& s ' 2j+l 2j+l ' '  2j+l  ' ]/
Assuming the division process is functioning properly, this is a direct conse
quence of the fact that  r < a < 7 when a 000 = 1.
The discussion of the limits on a = a.. , follows a similar pattern.
2j+l
* ■*
The bits oc , a , (X a. , a , OL , and OL are examined to insure that the true
sign of OC is know whenever a <  q or a > q. This discussed in more detail
later. The apparent sign of a is a © r\ where r\ = a JX ^ a a a a is the
apparent carry into the 1 position. If a. ,© r\ = 0, a must be positive. If
a _l© 'Hi = ^t a i s apparently negative, but the true sign may be positive due
99
to stored carries to the right of OC . It follows that the negative inner limit,
a =  o> determines the number of leading bits which must be examined to insure
that a zero quotient "hit" is predicted if and only if  q < a < q.
If OCJX J3t oc = 1, then oc , = 1, assuming the division process is func
tioning properly (i e , assuming the limits on the partial remainders have been
maintained). If a =0 when a a a a = 1, a must be greater than +1 and the
limits on the division process have been exceeded (i.e., an error of some type
has occurred ). Note that when ocjpcococ = 1, the adder relation guarantees that
OC = oc = 0« Therefore, under this condition the apparent sign of oc is negative,
but the true sign is positive if a string of units and a stored carry appear to
the right of a . As a final note, a a a a = 1 insures that  k < cc < rj. The
positive limit is the sum of the infinite stored carry representation shown be
low.
11 1
1 1.1 1 1 1 1...0 1 . . .
If a OC Oi oc = 0, the apparent sign of oc must agree with its true sign.
Any stored carry to the right of OC cannot be propagated into the 1 position.
Note that a may be in the range  ^ < oc < rr even though OC OC Ot oc = 0.
The function of the pMsS logic is summarized as follows. The apparent
* x
carry into the 1 position, t] = ^rP^n ^ ^c^i^o®?* determines the apparent sign
of a, CC © T) . The latter is compared with the true sign of the divisor, m
This comparison is formed as 2MsS  p=  © T l, in negative logic where
5 = OC m . The result of this comparison is valid if and only if the true
and apparent signs of oc agree. If oc oc oc a = 0, agreement is guaranteed, so
2MsS is selected if 2MsS  p = (i.e., if the signs of the dividend and divisor
agree), and 2MsS is selected if 2MsS  P = (i.e., if the signs of the dividend
100
and divisor disagree). If ocJXQLCt = 1, OMsS is selected, since the apparei
true signs of a may not agree. Even though OMsS is selected, the succeeding par
tial remainder cu . = a ^ • n is still within 2d < a~ . _ < 2d . If the div
2j+2 2j+2 ' '  2j+2  ' '
ision process is functioning properly, this result follows directly from the
fact that  q < a, < r when a a ,ai a = 1.
The maximum and mimimum values which the partial remainders may attain
is the last topic considered in this section. These values are used to deter
mine the number of bits to the left of the point that must be examined to ex
tablish the true sign of a or OL in all cases.
It has been shown that under steadystate conditions, the limits on
the unshifted partial remainders are 2 < < 2 and 1 < a < 1. However, this does
not guarantee that the limiting values can actually arise in practice. It is
shown below that more realistic limits on the unshifted partial remainders are
2 < a < I and _1 < a < T^.
Replacing a^ . _ by ~ . _, and s _, by Uql . . in the recursive relations,
2j+2 J °2j+2 2j+l 2j+l
we obtain
a 2j + l " °2j  y 2j d
°2j + 2 = ta 2j + l " 2y 2j + l d
Keeping the pMsA and pMsS logic in mind, we can now determine the maximum and min
imum values of a_ . . and ~ . '
2j+l 2j+2
The limits on OL . are determined by noting that a p .and y^.d have
the same sign if q a = and may or may not have the same sign if
a _l a O a i a p ~ *• However, in the latter case, we know that y =0. It is clear
that if a = and d = 111, then y^.d = 1 and QL . . = 1. In order for
2j ' " J 2j 2j+l
yp.d = +1, d must be 1 and a must be negative with , o n o^ cr p = 0. To make
■101
a_ . , as positive as possible, cu . must be the smallest negative value for which
2j + l ' 2j
a a n a, a = 0. This value is found to be  — • It cannot occur in the machine
because it has the infinite representation shown below.
111 1
0^ =111. 100101. ..01... = ^
Therefore, if Idl = 1, the most positive a_ . . must be less than 1  —  = r— .
1 ' ' 2j+l 12 12
The limits ona.. . are: 1 < a . n < ttTj and the corresponding limits on
2j+l  2j+l 12'
s~. , = ha^. . are: k < s . , < ==.
2j+l 2j + l  2j+l 13
To obtain the limits on ^ • n) we note that QL . . and y,_ . _. d have the
u 2j+2' 2j+l 2j+l
same sign if a (X oc oc = and may or may not have the same sign otherwise. If
ajXQLQL = 1, yv. _ = 0. The negative limit on a ^ ■ « occurs when QL, . , =0
12 3 ' 2j+l ° u 2j+2 2j+l
and d = 1, since a = U(o)  2 = 2, The positive limit occurs when
Idl = 1 and a. is the smallest negative value for which OLJX^OLJX = 0. This
1 ' 2j+l 12 3
value is  — and has the infinite representation shown below,
11 1
OL . , = 1 1.1 1 1 1...0 1 . . . =  7^
2j+l 12
If Idl = 1, the most positive «_. _ is less that k( — ) + 2 = — „ The limits
1 ' u 2j+2 '12 3
° n °2j + 2 = a 2j + 2 are: ~ 2 ^ CT 2j + 2 < 3'
11 5
It is interesting to note that OU . , = ttt and n. ^ = ^ are no "t steady 
2j+l 12 2j+2 3
state limits even if infinite representations were allowed. The limit
o . o  ? can b e obtained assuming a = — but not conversely.
d^+c. 2 j +1 12
The following examples illustrate how the limits on the unshifted par
tial remainders arise or are approached.
■102
Let the subnormalized divide!  nmi the normalized divisor be 
I
j =
1
AQ 
.
1
. . .
=
1
J =
+ M 1
1
1
.
. . .
=

1
y o =
1
j =
1
a
1
1 .
1
. . .
=
—
7
8
j =
SR 
1
1
, 1
. . .
=

1
2
j =
2M
1
.
. . .
=
+
2
y l =
1
j =
a •
1
1
. 1
. . .
=

3
2
j =
o
AQ i
1
1
. . .
=

3
2
j =
1
Mj
1
. . .
=
+
1
y 2 =
1
1
1
j =
1
a i
i
i
1
1 .
1
. . .
=

1
2
j =
1
SR i
1
1
1
.
. . .
=

2
j =
1
2M
1
1
.
. . .
=
+
2
y 3 =
1
!
j =
1
a ;
.
. . .
=:
o
j =
1
AQ i
.
. . .
=
j =
2
M
1
1 .
. . .
=

1
y h 
1
1
j =
2
a
1
1 ,
. . .
=

1
j =
2
SR
1
1
. . .
=

k
j =
2
2M !
1
. . .
=
+
2
y 5 =
1
;
1
j =
2
a
l
1
1
. . .
=

2 :
j
j =
2
AQ 
1
.
. . .
=

2
j =
3
 M 1
1 ,
. . .
=
+
1
y 6 =
1
1
j =
3
a !
1
1 .
. . .
=

i !
103
The negative limits of a = 2 and a = 1 clearly occur in this ex
ample, It is easily seen that the infinite quotient is
1
y = 1 . 1 1 11 1 1 1 1...1.
Let the subnormal! zed dividend by  rrr  2
divisor be 1,
J = 1
j = o
and let the normalized
J =
j = o
J = o
j = 1
j = 1
j = 1
j = 1
j = 1
j = 1
j = 2
j = 2
AQ
1
1
. 1
1
1
1
1 . . .
=
1
.288
OM
.
. . .
=
a
1
1
. 1
1
1
1
1 . . .
=
1
" 16
. 2 88
SR
i l
i
1
1
. 1
1
1
• 3
. . . .
=
1
 IT 
2 86
OM
i °
.
• •
. . . .
=
1
1
1
. 1
1
1
=
1
" k '
2 86
AQ
1
1
. 1
1
1
=
1
" k '
2 86
 M
1
.
=
+ 1
a
. 1
1
1
. .
. . . .
=
3
+ h 
2 86
SR
1
1
.1
1
1
1
, ,
• • »
=
+ 3 
2 8U
2M
 l
1
1
,0
. .
. , . .
=
 2
a
.1
1
1
1
=
1 
2 8U
AQ
.1
1
1
1
=
1 
2 8U
M
1
1
.0
=
 1
a
1
1
, 1
1
1
1
• •
• . . .
=
_ s 8k
y = o
JTi
7r
7 3 l
y k
= i
Although the last partial remainder shown in this example has a small
negative value, the pMsS and pMsA logic will predict zero quotient "bits" for
■10U
almost all of the remaining steps of the division process because OLJXOLXX = 1
and o c n c, a P = 1. It is clear that y = 0,0111000 . . . = + tt ^ n "this
example the largest value of a is approximately +1, while the largest value of
3
OL is approximately + f. Other examples using divisors slightly less than unity
in absolute value will yield unshifted partial remainders which are closer to
the limits of a = 5" aXi ^ a = To* There are no examples which yield unshifted
partial remainders that equal or exceed these limits.
Let crk = a n c n represent the apparent carry into the a , position.
Assuming a . a = 0, what are the smallest positive and negative values of
for which CT »+) crk does not represent the true sign of j ? The smallest
positive value is +2. It may assume either of the following forms under the
above conditions :
0100 0000
0001.0000...; 0010.0000...
The smallest negative value under these conditions is  I7. It has the fol
lowing infinite representation:
111 1
1 1 1.1 1 1 1 . . . 1...
Although this value cannot arise as an unshifted partial remainder, 2 certainly
can. It may assume a number of different representations for which a > © crk
does not yield the true sign of a • Two possible representations are given
below.
0010 00010
1101.110 0...; 1101.111100...
It is clear from this analysis that when a . ox Ch ch  ^, a , *d) crk ,
always yields the true sign of the unshifted partial remainder, a , when a >
■105
but fails to yield the true sign in certain cases when a < 0. To avoid this, it
is necessary to examine so © ^ where 1 2 = a_ 2 v o_ 1 o Q o  If c^Cq^o^ = ,
the smallest positive and negative values of for which so @ f] does not
represent the true sign are +h and 3z« J^ follows that s a © *) represents
the true sign of o when a , cua, a p = and 2 < a < fr.
Let ak = a v a a a a. represent the apparent carry into the a po
sition. Assuming a_a a a = 0, the smallest positive and negative values of a
23
for which a © Ok does not represent the true sign of a are +1 and  rr% Since
the unshifted partial remainder, Ot , may be 1, a © ak will not yield the true
sign of a in all cases when a a a a =0. To avoid this difficulty, it is neces
sary to examine a © tj where r\ = a a ^ (X (X (X (X . Assuming a a ^ a = °>
the smallest positive and negative values of a for which a © r\ does not re
23
present the true sign are +2 and l^r. Therefore, (X © T) represents the true
sign of a when aaaa = ° and 1 < a < *..
In the original design of the pMsA and pMsS logic, a © ak and
a n © ak were thought to represent the true signs of CT and a when a CT n a n cu =
aaaa = respectively. This error was pointed out by R. H. Farrell and cor
rected before layout was complete .
3 . 1 o IT The Quotient "Bit" Recoder and the BorrowSubtractor
The quotient "bit" recoder logic is shown at the top of LTa (D1507).
It is used only during division to recode successive quotient "bits", which are
held in G , H , G , and H into base k quotient digits. At the output of the
recoder, the quotient digit is represented by q. = _J +P[,p + 2 Pk"3 '" p kL where
= 0, 1, 2    22 or 23 and 3 < q < 3. (The q. does not refer to the out
J J
\ *
put of the Q. Felement.j The bits f\ 9 , P^o* an ^ i Pi u are transferred to R^ p ,
R, , and R, , respectively when gR = 1, § = 1, and 5 = 1, indicating that a
divide order is being executed. (See D152U, D1272, and D1295.)
•106
In the table shown below, y p . is the quotient "bit" held by G ,11 ;
2J
y is the quotient "bit" held by G ,H . The sign comparison signal, 7,
generated by the logic discussed in section 3«1»H« 7 = 1 when the true signs
of A,Q (e.g., the shifted partial remainder) and M (e.g., the divisor) disagree,
2y 2j + l
y 2j+2
7
q j
P l+2
PU3
p ^u
2
1
e
3
1
1
2
e
2
1
1
2
1
e
1
1
1
1
1
e
1
1
1
1
1
1
1
e
1
1
2
1
e
1
1
2
e
2
i
!
1
2
1
e
3
1
1
The e symbol denotes either a "1" or a "0" , and j = 0, 1, 2 22 or 23
From this table we obtain the following expressions:
Pj.o = te^.i =  2 )  (2y ,..  0)(y o4iO = 1)
'1»2
2j+l
2j+l
2j+2
 (2y 2J+1 = 0)(y 2 . +2 = 0)( 7 = 1)
Using the Boolean expressions for y and y as given in the preceding
section, we obtain:
$1 =gh ^hffh ^hh'y
h2 &1 n ± "L^ig ^ x ^ 2 7
P^ 3 = C^2j + i ^ 2)
(v = O) v (y = l)
^2J + 1 = 2)
(2y 2j+1  0)(y 2 . +2 = 1)
L (y 2j + 2 = 0) v (y 2j + 2 = 1}
•107
follows that
P U 3 = S l h l h 2 V g 2 h 2
v h x g 2 h 2 v g 1 hJ h 2 v g 2 h 2
= hl h 2  h x g 2  h;L g 2 h 2
P ^ = (y 2j + 2 = _1) V (y 2j + 2 = 1}
This yields
= h_
P^ = n 2
In the preceding section, it is noted h  1 implies g = 1, and
h  1 implies g = 1 except during the D9 control step. Therefore, we can
say Sphp  during D9 and Dll, and g h =0 during Dll. Examination of the
above expressions for f3, , p> , and p, > shows these identities would not pro
duce any simplification of the recoder logic even if the hardware necessary to
insure g,h =0 during D9 were added.
The "borrow subtractor logic appears on the upper half of SEC (D1527).
It is used only during division to convert serially the base h representation of
the quotient (3 < q. < 3) to the usual binary representation. If the quotient
"bit" recoder produces a negative base h quotient digit, R. is set to "1"
when gR = 1, The borrowsubtractor propagates this borrow over the Rj _ and R,
positions. The outputs of the borrowsubtractor are defined in the table shown
below.
■108
kl
V k2
T h 2
\l
\
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The corresponding Boolean expressions for d, and d, follow
d Ul = r Ui r l2 v r Ul^2 S/ ^A 2 r L
— x — x
\ 2 = r U2 r U2 ^ r ^2 r l+2
The second line of the table shows a unit subtracted from zero in R,
and R, yields three as a result (i.e., d, = d, = l). This is meaningful if
there is a unit in the R, position before the subtraction and a zero afterwards.
Theoretically, this is precisely what happens even though the borrowsubtractor
does not examine an output in the R< _ position. For the present, we shall assume
the existence of an "Rh n " Felement which always contains a unit when r, = r, =
■x
and r>p = 1, but contains a zero otherwise.
* " *  
The quotient "bit" recoder, borrowsubtractor, and Q< = r \ i o r hy r hh
(see sections 3.1.2.11 and DI52U) operate as a unit to form the fractional
quotient in binary representation in the R and Q registers during control steps
D7, D9, D10, and Dll. The function of this logic during the formation of a
fractional quotient is now examined.
In control step D6 (see D1128 or D1272) the normalized dividend in
A, Q is shifted right into S,R placing the two least significant bits in R«
■109
and R; i . At this point in the division sequence, R, and 0, both contain "0" and
5 =5=0, Since the order is division and not multiplication, u = 0. Hence,
the inputs to R. and Q, as defined in sections 3.1.2.13 and 3.1.2.11, are "both
zero. OMsS is selected, which implies the quotient "hit" y = 0. This is a
consequence of subnormalizing the dividend to obtain a fractional quotient in
the range 1 < q < 1, The signal gH goes to "0" in D6 to set H to "1" which
agrees with the selection of OMsS and y  0. The most significant half of the
initial unshifted partial remainder appears at the output of the Sadder. The
most significant bits of this output feed the pMsA logic.
In D7, the subnormalized dividend or initial partial remainder is
gated straight into A, Q. The two least significant bits go into Q, _ and Qkk.
The p,MsA signal goes to "0", which permits the pMsA logic to select MsA, OMsA,
or MsA and set G_ and H accordingly. It also permits the contents of G, and
H to be gated into G and H . Following these operations, the output of G
and H represents the y quotient "bit" which may be 1, 0, or 1. The output
of G, and H represents the y quotient bit which is zero, since h =0.
Note that g may be "1" or "0" depending on the contents of G during the final
pass through Dll in the last divide operation . The most significant half of the
first unshifted partial remainder appears at the output of the Aadder. The most
significant bits of this output feed the pMsS logic. The quotient "bit" recoder
generates the initial base h quotient digit, q = +1, 0, or 1, according to the
outputs of G, , H , G and H ,
Since h 1 = 1, q Q and y Q agree. If y Q = 1, P^ = 1, p^  1, and
%k = 1 ' If y = L ' P U2 = °^ P ^ 3 " °^ and p kh  1 ' If y = °^ ^2 ' 7 ' % " °'
an< ^ P UU = ^° ^Up = '^ = 1 if "the true sign of the subnormalized dividend in A,Q
disagrees with the sign of the divisor. Thus, if o cu a cu = 1 and the true sign
of a disagrees with m , , a zero quotient "bit" is predicted (y = 0), but a
negative quotient bit will eventually arise. However, the value of p. p is not
■1.10
TV
ant on this initial step. It is not gated into R^ p during D9 because
8 = as explained below.
The first unshifted partial remainder is shifted left into S,R during
D9. The two least significant bits are gated into R< , and \ . The 6 signal
goes to "l" allowing p. and p., to be gated into R, and R, , respectively.
The logic associated with the 8, signal appears in the D9 section of D1272.
The point at which this signal controls the inputs to R« „ and R, , is shown in
the right center section of D152U. The A EcclesJordan is still set to "0"
(i.e., 8_ a 0), so a "0" instead of (3, _ is gated into Rr  The reason for this
is given in the next paragraph. The p MsS signal also goes to "0" in D9, per
1 t
mitting the p MsS logic to select 2MsS, OMsS, or 2MsS and set G and H, accord
ingly. Since the output of the quotient "bit" recoder is still influenced by
the contents of G and H at this point, the need for G and H, is apparent.
The most significant bits of the second unshifted partial remainder appear at
the Sadder output and feed the pMsA logic.
Control now passes to the iterative loop of the division sequence
(D10 and Dll). We consider the first pass through the loop.
When D10 is activated the first time, the second unshifted partial
remainder is gated straight into A,Q. Since R, was set to "0" during D9, the
outputs of the borrowsubtractor, d, and d, , simply reflect the two least sig
nificant bits of the partial remainder which are gated into Q, and Q^ p . Like
wise, the first two bits of the quotient in R, and R, , are gated into Q, and
Qi 1 . If the first base h quotient digit is 1, both R, and R . contain a "l".
Unless these bits are modified by the borrowsubtractor during the first pass
through Dll, they will become the negative sign bits of the fractional quotient.
Similar statements apply for q = and +1. Q, is set to since R, =
and u = 0. If R. were set to "l" during D9, the two least significant bits
111
of the first partial remainder would be modified by the borrowsubtractor during
the first pass through D10, This is why A is not set to "l" until control
passes to D10. The p MsA signal goes to "0" during D10 and allows the pMsA
logic to select MsA, OMsA, or MsA and set G and H accordingly. It also gates
i t
the contents G, and H into G and H . The third unshifted partial remainder
then appears at the output of the Aadder and in the first hk bits of Q,
During the first pass through Dll, the third unshifted partial remainder
is shifted left into S,R placing the two least significant bits in R and Rr n .
The unmodified sign bits of the quotient which correspond to q n are gated into
R, and Ri^* The outputs of the quotient "bit" recoder are gated into R^ Q , ^h?'
and Rj i since 5=5=1. A "0" is gated into R, unless the base h quotient
digit q is negative or zero with y = 1. The p MsS signal goes to "0" which allows
the pMsS logic to select 2MsS, OMsS, or 2MsS and set G and H accordingly. The
fourth unshifted partial remainder appears at the output of the Sadder and in
the first h2 bits of R.
When D10 is activated the second time, the fourth unshifted partial re
mainder is shifted straight into A,Q with the least significant bits being placed
in Q, and Q^ . The bit configuration in Q^ , Q^ 2 , Q^, Q^ , and Q^ is consid
ered below. The p MsA signal goes to "0" and allows the pMsA logic to select
MsA, OMsA, or MsA and set G and H accordingly. This also transfers the con
t i
tents of G, and H to G and H „ The fifth unshifted partial remainder then ap
pears at the output of the Aadder and in the first U2 bits of Q.
If R« p contains a '0" during the second pass through D10, the first
four bits of the quotient in R^,, \o) %v and ^UU are S 3 ^ 6 ^ straight into Q, ,
%2> %3' and \k' A "°" iS gat6d int ° %2'
If R^ contains a "l" and either or both of R, and R,, contain a "l",
the base h quotient digit q is negative. The outputs of the borrowsubtractor
112
(d, ,d, ) are (0,0), (l,l), or (l,o) depending on whether q = 1, 0, or 1. If
cu = 0, R, and R, both contain "0" and the borrow is false. However, in this
case the outputs of the borrowsubtractor (l,l) are gated into Q, and Q, as
the sign bits of the negative quotient. Since either or both of R. and R. . con
tain a "1", a "0" is gated into Qj, p . The contents of R, and R, , are gated
straight into Q, and Q, a s usual.
If R> contains a "l" and R, and R, . both contain "0" during the sec
ond pass through D10, q is zero but the true sign of the second partial remainder
disagreed with the true sign of the divisor. Note that the second partial remain
der is gated into A, Q, during the first pass through D10. In this case, a borrow
is initiated in anticipation of a future negative quotient digit. Even though
a zero quotient digit is predicted, a negative quotient digit will eventually
arise in the infinite representation of the quotient because 7=1. Since the
borrow which accompanies a negative quotient digit can only be propagated over
Ri , and R, during the transfer from R to Q, it is necessary to initiate a bor
row from the bits in R, and R, as soon as a zero quotient digit is placed in
R, and R, , with y = 1. In view of the fact that 22 or 23 zero quotient digits
may be generated before the negative quotient digit appears, the borrow from R,
and R^o must be held as a stored carry in Q. . Therefore, if the division pro
cess terminates before the negative quotient digit is predicted, the stored carry
is transferred to S, by the interchange in D17 and added to the quotient by the
S and A adders. Returning to the second pass through D10, the outputs of the
borrowsubtractor are gated into Q, and Qk p « Q^o = 1 in this case, so a "l"
is gated into Q^p* The zeros in R, and R, , are gated straight into Q> and Q, ,
as usual.
The significance of the theoretical "Rh n " Felement is now apparent. If
this element existed, it would receive the stored carry that is placed in Q,
k2
113
when a zero quotient digit is predicted with 7 = 1. For example, assume the fol
lowing bit configuration in R during the second pass through D10 where x and y
represent the two least significant bits of the partial remainder.
V* "  n r*  l
r 39  x r k0 = y v kl = r U2 = ° r k3 = r kk = °
The resulting bit configuration in Q during the second pass through Dll is given
below.
%2 = 1
q 39 = X ^0 = y %1  X %2 = 1 %3 = ° %k = °
Assume that a zero quotient digit is placed in R. and R, , during the second pass
through Dll. Since Ri was set to "l" under the same condition during the first
bit configurations in R and Q appear below,
pass through Dll, 7 must still be "l" so R, is again set to "l". The resulting
"4"  * 4 al
r 3T :: X r 38 = y r 39 = X T h0  X r >+l = °
d 37 = X q^ = y q^ = 1 q^ = 1 %± = 1
r U2 = °
^3 = °
r UU = °
%2 = X
V * X
1U3 = °
\K'°
* . .. *
It is clear that the borrow in R, is actually subtracted from V'r, " + 2r, + r> _
It is also clear that the "R, " Felement does not have to exist physically. If
*
we assume a 1 quotient digit is placed in R, , R, , and R. > during the second
pass through Dll, the resulting bit configurations in R and Q are as follows:
"  1 l
r 37 = X r 38 = y r 39 = 1 r liO = 1 L = ° :> = ° r 'i3 = T kU '
X
%2
=
q 37 = X q 38 = y q 39 = 1 %0 = 1 %l = 1 %2 = 1 %3 = 1 %h = 1
This pattern of activity is typical of the remaining steps of the di
vide loop. During each pass through Dll a "l" is gated into R. p if the quotient
"bit" recoder generates a negative "base k quotient digit or a zero digit where
the true signs of the partial remainder in A,Q and the divisor in M disagree
(i.e., where 7=1). In either case during the next pass through D10, a unit is
borrowed from V'ri " + 2r, + r. to yield 2d, i d, which is gated into Q»
and Qk q . In the former case, the borrow is absorbed by the negative quotient
digit that was placed in R) , Ri , and R, , so \,n i s se ^ "to "0". I n the latter
case, a zero quotient digit was placed in Rr 9 , ^hot anc ^ ^hh so ^^ e borrow i s held
as stored carry in Q, . If the quotient "bit" recoder logic generates a posi
tive base h quotient digit or a zero digit with 7=0 during any pass through
Dll, R, is set to "0". A borrow from the bits in R, and R, does not occur dur
ing the next pass through D10, and 0^ is set to "0". Even if a string of zero
quotient digits are generated, 7=0 implies that the next nonzero quotient digit
will be positive .
During the final pass through Dll, the p„MsS signal goes to "0" allow
! t
ing the pMsS logic to select 2MsS, OMsS, or 2MsS and set G and H accordingly.
The final base h quotient digit is placed in R« , R, , and R. . . Note that this
1 1
digit is independent of the excess quotient "bit" held in G and H . The divide
loop terminates and control passes to D12.
The partial remainder beyond the final partial remainder appears at
■115
the output of the S adder during D12. It is gated straight into A so its true
sign may be compared with the sign of the divisor via the KgA request and the
carryborrow logic as explained in section 5.13. The output of the carry borrow
logic corresponds to 7 at this point. It is gated into the CB Felement and
used together with the excess quotient "bit" in G, and H, to determine quotient
roundoff as described in section 5.13. The latter occurs in D17 while the
corresponding remainder correction occurs in DlU.
The final unrounded fractional quotient appears in R during D12. If
h2
R, contains a "l", the Ul — and k2 — bits of the quotient are modified by the
borrowsubtractor during the straight transfer into Q. Q« is set to "1" if the
last quotient digit is a zero and Ri _ is set to "l". This represents an unused
borrow which is absorbed as a stored carry by the S and A adders following the
interchange in D17.
This completes the description of the quotient "bit" recoder, borrow
subtractor and associated logic. Note on D1272 that 5.. goes to "0" during D12.
A ? is set to "0" during Dlk. For a description of the complete division control
sequence the reader is referrec to section 5.13.
3.2 The Exponent Arithmetic Unit
The general structure of the EAU is shown in Fig. 6. The EA, ES, EM,
and E registers each contain 8 bits as shown below.
EA^, EAg . . . EA i . . . EA Q
ES„, ES/ . . . ES. . . . ES^
EM^ EMg . . . EM i . . . EM Q
E 7 ' E 6 * * * E i * ' * E
The EAU does arithmetic modulo 256. The point lies at the right end
116
ill registers the i — bit having a weight of w except the "( — bit v.
,th
7
has a weight of 2 .
An 8 bit adder (Dadder) with an optional carry into the — position
provides the capability of doing exponent arithemetic and counting. It accepts
the outputs of the EA register and the sD selector as inputs, and yields a sum,
d, which can be placed in ES via gES or in E via DgE. The value of d as function
of em and ea under various selector and carry input settings is given below.
c =
c = 1
EMsD
d =
ea +
em
d =
ea +
em +
1
Note: The small c
EMsD
d =
ea 
em 
• 1
d 
ea 
em
denotes the true
2sD
d =
ea +
2
d =
ea +
3
output of the C
OsD
d =
ea
d =
ea +
1
status memory ele
2sD
d =
ea 
2
d =
ea 
l
ments.
22sD
d =
ea 
22
d =
ea 
21
In contrast with the MsA and MsS selectors, the request for EMsD does
not automatically yield a carry input to the lowest order position such that
d = ea  em. DC must also set C to "l" or "0" depending on whether d = ea  em
or d = ea  em  1 is desired at the adder output.
The selectors sEA and sE control the input to EA via gEA and the in
put to E via gE. The new contents of these registers following activation of
the appropriate gate are listed below.
EsEA:
e
S M >EA
EMsE:
em^>E
ESsEA:
es
^>EA
OsE:
0^>E
OsEA:
£^>EA
6sE:
6 ^>E
21sEA:
21
^>EA
22sE:
22 ^> E
During the decode step (Gl) a zero or the contents of E is transferred
to EM via FlgMEM. The sign bit of the incoming exponent IN, is always gated
■117
o w
•H
& >
k4
w
L>n
a
T
CO
vo
V
H
O
u
1
i
Dec
Memo
M)
I*"
Exponent
with
(ED
3
w
ESsEA; EsEA
OsEA; 21sEA
3
i.
LJ '
I
I
I
lo
o
O « Q O P Q
W W W W
I
a
+>
•H
I
o
O H S
■118
into both EM, and EM . The D adder is used to determine d = ea  em  1 i n
floating addition, ea + em in multiplication, ea  em in division. It is also
used in conjunction with the EA and ES or E registers for counting the number
of shifts in floating addition and the number of iterative steps in multiplica
tion and division. At the end of a DC operation the exponent of the result is
left in E. At the end of divide orders the exponent of the quotient is in E and
the exponent of the remainder is in ES.
In performing a DC store order, the exponent of the operand to be stored
is placed in ES and then transferred to the last 7 bits of the OUT register dur
ing the S9 step of the store sequence (Flow Chart D1128). Whereas 128 < x < 128
is allowed inside the EAU, only exponents in the range 6K < x < 6h can be stored
with f. If x is stored alone as in SEX, es„ is mapped into IN_ Q , IN, ... IN, ,
IN^ with esg — > IN^ , es — > IN,g ... and es Q — > IN . Using SEX,
128 < x < 128 can be stored as a quarter word by AC. Note that the sign bit
is duplicated in the six most significant bit positions of this quarter word.
The bits of f that normally occupy these positions are overwritten during the
transfer of R and ES to OUT. This feature is discussed in greater detail in
section 3.1.2.1U.
The strictly exponent orders complement the SEX order. Even though
IN is copied into M and EM during the decode step as previously described, the
first step of ADE, SDE, CAE, and CSE copies M, , into EM^. Thus, if one is
willing to use a 13 bit quarter word and ignore the fractional part or store
it separately, storage and retrieval of full 8 bit exponents is possible.
The EAU decoder is a large block of logic whose inputs are the outputs
of the Dadder. Its purpose is to detect specific values and ranges of the
adder output. Knowledge of these values is used in the execution of the float
ing add and shift instructions . They are also used to determine the end of a
119
count. Detection of whether the output is inside or outside the range
6k < x < 6U is also accomplished at this point. Since knowledge of the pre
vious range or value of d must be remembered during the time the inputs to the
adder are changed, gES or DgE will gate the outputs of the EAU decoder into a
register called ED. The memory elements of this register are named according
to the range of d they represent. For example, the ES > memory element is
set to the "1" state (i.e., set so that its 1 or true output is a positive volt
age) by gES or DgE if d > is true. If d < is true when gES or DgE is on,
the ES > memory element is set to the "0" state,
3.2.1 A Summary of the EAU Logic
The registers and selectors of the EAU are shown on the drawing by
the same name (D1502). The eight bit adder associated with the EAU is shown
in block form on the EAU drawing and in detail on the EAD drawing (DI503).
The exponent decoder logic as shown on EDM (DI50U) is considered a part of the
EAU, The outputs of the exponent adder feed the decoder as indicated by the
central table on the EAU drawing.
3.2.2 The EAU Bit Path Logic
The bit path logic of the EAU is described first. As in the MAU, the
description is register and selectororiented including the connections with
the Fl (IN) and F0 (OUT) registers of the Flow Gate Memory, The descriptions
of the 8bit full carry adder and the exponent decoder follow in order,
3,2.2.1 The Fl to EM Path
The inputs to the EM register are shown at the top of the EAU drawing.
When FlgMEM = 1, Fl, is gated into EM^ and EM.^ while F, ^ through F are gated
•120
into EM through EM respectively. As shown in Fig. 6, there is a path from ES
to EM. When ESgEM = 1, es„ through es are gated into EM, through EM respective
ly. Note that mn is gated into EM.^ when m, , gEM^ = 1. This is shown in the up
per left corner of D1502. The first step of the (e) sequence is the only con
trol step which causes this transfer. (See section 5.6.)
3.2.2.2 The EM Register and the EM = 6k Logic
The EM register is loaded as indicated in the preceding section. Its
outputs feed the sD selector which is described in the following section and the
sE selector which is discussed in section 3.2.2.7.
The true output of EM, and the complement outputs of EM through EM
feed an AND shown in the top center of the EAU drawing.
(em = 6k) = (emg)(em )(em 1+ )(em )(em 2 )(em 1 )(em Q )
It is clear that the output of this AND has unit value only when EM contains
+ 6k. (The point in the EM and all other EAU registers is assumed to lie to
the right of the — bit.) Since this detector is used by DC only when EM con
tains an inrange exponent from memory ( 6k < em < 6k), its output is called
(em = 6k) .
3.2.2.3 The sD Selector
The outputs, eb., of the sD selector feed through difference amplifiers
(shown at the bottom of the EAU drawing) to the 8bit fullcarry exponent adder
(D adder). The eb„ and eb„ signals also feed the exponent decoder. Shown be
low are the Boolean expressions for each bit position of the selector,
eb. = em.(EMsD) v i^. (EMsD)
i i l
< i < 7
121
eb„ =
etv =
eb_ =
eb, =
eb.
eb^ =
eb n =
eb
V f
t
eb 6
V (
eb 5
\s (
t
N/ (
eb 3
\y (
eb 2
\/ (
e \
\/ (
22sD) s/ (2sD)
22sD) v/ (2sD)
22sD) ^ (2sD)
2sD)
22sD) v/ (2sD)
2sD)
22sD) v/ (2sD) v (2sD)
eb
eb
When the sD selector mechanism is set to OsD, EMsD  EMsD = 2sD = 2sD =
In contrast with the MsA, MsS, and 2MsS settings in the MAU, EMsD does not auto
matically cause the complement carry to be added to the least significant posi
tion of the difference. In the EAU adder (D adder) this carry is the true out
put, c, of the "complement carry" status memory element C (DI285). If EMsD and
C are true during a particular control step, then ea  em  1 appears at the D
adder output. If EM and C are true, then ea  em appears at the output.
The D adder can be used to count up or down on the contents of EA by
one or two units per pass. This is accomplished by a choosing of the proper com
bination of 2sD or 2sD and C or C. For example, ea  2 appears at the output of
the D adder when 2sD is selected and C is true. This type of count is used to
control the number of passes through the inner loop of the multiply sequence
(M5 and M6).
The 22sD setting is used in only three control steps  kh, S10, and
D17. If EA contains the exponent of the accumulator, AQ, then ea  22 is the
exponent associated with the positive fraction contained by Q where the radix
point lies to the left of q._..
■122
3.2.2.U The sEA Selector
As shown at the bottom of the EAU drawing, the sEA selector controls
the input to the EA register. The Boolean expressions for the outputs, EA.,
are given below.
EA. = es.(ESsEA) v e.(EsEA)
1 i v 1
< i < 7
The es. and e. signals are the true outputs of the ES. and E. Felements respec
tively.
EA = EA*
EA 6= EAg
EA r = EA'
5 5
EA. = EA. ^ 21sEA
EA = EA*
EA = EA ' v 21sEA
EA = EA'
EA = EA v 21sEA
When OsEA is selected, ESsEA = EsEA = 21sEA = 0. The 21sEA setting
is used only in the M2 control step. The need for this additional selector op
tion arose as a consequence of the way in which the count for the inner loop of
multiply is handled and the desire to make the multiply sequence as fast as pos
sible.
3.2.2.5 The EA Register
When gEA = 1, the output of the sEA selector is gated into the EA
■123
register. The outputs of EA, ea., feed the exponent adder which is described in
section 3.2.3. (Note on the EAU drawing that portions of this adder are on four
chassis  A6R, A7R, S6R, and S7R. ) The ea„ and ea signals also feed the expo
nent decoder.
3.2.2.6 The ES Register and the ES to FO Path
As shown in Fig. 6, the only signal inputs to the ES register come
from the exponent adder. When gES = 1, the adder outputs d through d , are
gated into ES through ES respectively. When 6kgES = 0, the ES register is
cleared to 6k. As shown on the EAU drawing, the value to which each ES
i
Felement is cleared is indicated by the side on which the 6UgES signal enters.
The outputs, es„ through es , feed the sEA selector and the EM regis
ter as described above. Outputs es/ through es are gated into E0, through
FO when RESgFO = 1. When SEX (store exponent) is executed, the es„ signal
is used to overwrite r through r, , causing es to be gated into FO through
FO.. when RESgFO = 1. (See section 3.1.2.1^.)
The es 7 and es/ signals are used to generate es (+) es/ as shown at
the left center of the EAU drawing. This new signal is used only in the con
ditional logic of S9. It has unit value whenever the contents of ES lie outside
the interval: 6k < es < 63. Any exponent outisde this interval is considered
overflowed with respect to Flow Gate or Core Memory. Thus the "overflow" status
memory element, 0V, is set when es„ @ es/ = 1; the store order being executed
is not logical, ^ = 1; and the number being stored is not zero (i.e., RZ = z = l).
3.2.2.7 The sE Selector
The sE selector appears, at the middle of the EAU drawing. The Boo
lean expressions for the outputs of this selector, E. , are given below.
■12^
E. = em. (EMsE) < i < 7
1 i  —
The em. signal is the true output of the EM. Felement.
E 7
—
E T
E 6
=
E 6
E 5
=
E 5
\
=
E u"
22sE
E 3
=
E 3
E = E v 6sE v 22sE
E. = E v 6sE ^ 22sE
E = E
As usual, when OsE is selected by DC, EMsE = 6sE = 22sE = 0. The
6sE setting is selected only in the PI step of the P sequence when SIA is exe
cuted. The 22sE setting is selected by only two control steps: PI for SIF,
and D6 for any divide order.
3.2.2.8 The E Register
As shown at the center of the EAU drawing, the E register is composed
of doublegated Felements. The outputs of the sE selector, E., are gated into
the E register when gE = 1. When DgE = 1, the outputs, d. , of the exponent
adder (D adder) are stored in the E register.
The d. outputs can be gated into either the ES or E registers by turn
ing on gES or DgE. If DgE = gES = 1, d. is stored in both ES. and E. simultan
eously (although somewhat more slowly). The arithmetic operations in the EAU
are so arranged that DC never does this duplicate gating. Even if it should
125
tecome desirable at some future date, it is not recommended because the fanout
capability of the d. would be overloaded in certain cases.
As indicated by the EAU drawing, the E register outputs, e., feed
the sEA selector only.
3.2.3 The Exponent Adder (DAdder)
The exponent adder (D adder) shown on EAD (DI503), operates over
eight bits and has full carry assimilation. It is designed for high speed and
large fanout. The contents of the EA register, ea, the output of the sD select
or, eb, and the outputs of the "complement carry" status memory element, C, are
its inputs. The sum of these inputs is represented by the d output in twos com
plement form. This output feeds the ES and E registers as well as the exponent
decoder which is duscussed in the following section.
The adder is essentially composed of two ranks of modulo 2 adders and
an 8bit carry generator. The first rank of modulo 2 adders form ea. (±) eb. .
These signals together with others form the carry, c, into each position. The
second rank of modulo 2 adders form the sum bits, d. = (ea. ©eb.) ©c. For
' l 1 11
use in the exponent decoder the complement sum bits, d. = (ea. ©eb.) (s) c.,
are also formed. Restoring logic is used to form both d. and d. to provide
adequate fanout and voltage level at the input to the exponent decoder.
The Boolean expressions for the adder as shown on EAD are given below.
First Rank of Modulo 2 Adders
w. = (ea. )(eb. ) v (il )( e b, ) < i < 7
1 11 ii — —
Carry Generation Logic
u. = (ea. )(eb. ) < i < k
111  
v. = (ea. ) v/ (eb. ) < i < 6
1 v 1' 1  
126
In the expressions which follow, u. and v. may he further designated by a or
b. This is the means used to distinguish between two signals which are logical
ly identical but electronically different. For example, in the lower right hand
corner of the EAD drawing u  a and u  b are equivalent logically but are
formed with two separate nonrestoring AND circuits. This was done because the
required fanout for the u signal exceeded the maximum of three for a nonrestoring
circuit. In the interest of speed, two nonrestoring AND s were used in place of
one restoring AND.
u = U V v u
u 23 2 3 3
V 2 V 3 = ^ v 2 " a ^ v 3
w 3% = W 3 V ^
V5 = V 5
U U 5 = V5 v ( ea 5 )( eb 5 )
These miscellaneous signals are now used to form the carry into each position,
c = c (True output of the C status memory element)
C =CV v [11  h)
1 v ;
C 2 = °0 V 0^ V 1 " ^) v ( u " b )( v x  b ) ^ u x
C 3 = Vo^l " b )( v 2 " b ) ^ ( u " a )( v i " a ^ v 2 " b ) V U 1 W 2 V U 2
C k = C W W 1^ Y 2 V 3^ V ^ U " a ^ v l " a )( v 2 v 3 ) v ^ U 1 V 2^ V 3 ^ U 23
c 5 = c i( v i " a )( v 2 v 3 )v ii " ^ u i v 2 )(v 3\^ " U 23 W U V \
c 6 = c 2 (v 2  a)(w 3 v u )v 5  ^3 ( V 5 ) V \5
C T = c 3 (w 3VV6 v u 3 ( V 5 )v 6 v u kf6 v u 6
■127
Second Rank of Modulo 2 Adders with Complements
d. = w. © c. < i < 7
l li — —
d. = w. (=)c. < i < 7
l i v l  
To resolve the complex appearance of the carry generation logic, re
move the "a" and "b" designations and substitute the expressions for the miscel
laneous signals. The resulting expressions for the c. contain minterms having
a mixture of v. and w. variables. Replacing all of the v. by w. or vice versa
11 11
would still yield a set of correct expressions for the c. . This follows because
th
a carry generated in the i — position, i.e., u. =1, is propagated into the
(ij) — position (j > 0) if either w = 1 or v = 1 for all k in the range;
k k
ij < k < i. The possibility of using either w. or v. in the carry generation
logic was pointed out by M. Faiman. The mixture of w. and v. signals that is
used was determined largely by fanout limitations and the desire to keep the tran
sistor cost at a minimum.
3.2.U The Exponent Decoder
The logic for the exponent decoder is shown on the EDM drawing (D1501+).
Its inputs are ea_,, eb , and the outputs of the exponent adder. In addition,
the gEA, gES, and DgE signals are used to gate information into Felements
which indicate something about the range of the D adder output. The S7d input
is used to set the ES < 6k Felement into the "l" state whenever the ES regis
ter is cleared to 6k during the S7 step of the store sequence.
With the exception of EDC, the Felements shown on the EDM drawing
form the "exponent decode" or ED register. The decoder outputs (e.g., d = 2)
set the ED Felements (e.g., ES = 2) when gED = 1. Note that gED = gES v DgE.
The outputs of ES = k, ES = 0, ES = 1, and ES = 2 are combined and
128
gated into EDC when gEA = 1. The EDC output, edc, is used in the conditional
logic of the A9 control step. Both ES = k, EDC, and the logic associated with
their inputs vere added to the original design of the decoder to provide slow
and fast modes of operation for the add loop (steps A9 and AlO). (See section
5.5.)
The outputs of the exponent decoder and the ED register are used pri
marily in the add loop (A9 and AlO) and shift loop (Fl and F2). However, be
cause the range of the D adder output is used so often to direct the action of
DC, the decoder outputs are cabled to many other areas . Excluding the add and
shift loops, one or more decoder or ED outputs are used in Al, A2, A3, A8, D7,
D10, D13, F5, K2, M3, M5, M6, MT, PI, R2, S5, and S7.
The Boolean expressions for the decoder are given below. For the most
part, these expressions were established by M. Faiman. The logic is developed
as shown on the EDM drawing moving left to right from input to output. It is
left for the reader to verify that the final outputs indicate the conditions
their signal names imply, e.g., (d = 0).
First Row
(ea^) ^ (eb^) = (ea^)(eb^)
(ea )(eb ) = (ea )(eb )
(ea ) v (eh) = (ea )(eb )
(ea )(eb ) = (ea )(eb )
\
> Cable Outputs
The numbers used to name the signals defined below (e.g., No. 21 )
have no significance with respect to values or range of values of d which the
Boolean expressions define.
•129
Second Row
No. 21 = cL (Used to increase fanout)
No. U2 = ^cL (Used to increase fanout)
No. 16 = d" 5 v d^d v d^d" 2
No. 17 = d u v d 3 d 2
No. 18 = d^ ^ d d 2 v dl
No. 22 = d u  dd^ ^ d 3 d 2 d Q
No. 2U = d 6  d 5  d^d 3  d 1 d 2 d 1
No. lU = d 5  d u d 3 v d^dgjV d 1+ d 1 d
No. 25 = No. 28 = No. 29 = (Ldgd d^d d 2
No. hk = d_ (For fanout)
HO. 15 = d g  SJV&VO
No. U3 = d_ (For fanout)
No. 26 = No. 30 = idldld 2
No. 31 = d (For fanout)
(df = l) = O, v dg v d v d^ v d v d 2 v d^ v d Q
The latter expression gives a "fast" indication of when d = 1. It
is sensed only during the inner loop of the multiply sequence. Negative logic
is used (i.e., (df = l) = when df = l) to conform with the negative logic
which is used throughout Delayed Control.
Third Row
No. 37 = (d = 1) = d 1 d (} (No. 29)
130
No. 33 = (d  3) = ^(No. 28)
No. 3U = (d < 3) = d v d 1 (No. 28)
No. 39 = (d = 0) = d Q (No. 26) (No. 3l)
No. 36 = (d = 2) = d^No. 29)
No. 9 = (l+5dl+l+) = (1+5 < d < 1+1+) = d 6 (No. 16) (No. 1+2)
v dgd^d d (No. 1+2) v dg(No. lU)(No. ^1+)
No. 35 = (d < 2) = d v d 1 d Q (No. 29)
No. 32 = (d = 10 = d d Q (No. 28)
No. kO = (d = l) = d Q (No. 30)(No. 31)
No. 1+1 = (d = 2) = d 1 d Q (No. 30)
No. 38 = (d > 2) = cL v (No. 30) (No. 31)
gED = ( g ES)(DgE)
Fourth Row
No. 31 = (fa5) = [(ea v eb )](No. 2l) v dg(No. l6)(No. 1+2)
 [(ea 7 )(eb T )]
fa5 = 1 implies that d > 1+1+ This means that fa5 = 1 if d is overflowed, i.e.,
when the true value of d is > 128.
No. 5 = (fal)  d [ea v eb T ] ~ d d 6 (No. lU) v [(ea^eb^]
fal = 1 implies that d < 1+6. This means that fal = 1 if d is underflowed; i.e.,
when the true value of d is < 129.
No. 19 = (faU) = & r v d^(No. 17) ~ d" (No. 18) n/ (No. 21 )
fai+ = 1 implies that 22 < d < 1+3 .
131
No. 23 = (fa2,3) = d 6 (No. 21 ) v d (No. 2l)(No. 22) v cL(No. 2*0
fa2,3 = 1 implies that U5 < d < 21,
These four signals are used in the Al step of the add sequence to
filter the appropriate case of floating point addition. (See section 5.5)
No. 11 = dov = [(ea ) v (eb )] v (No. U3)
No. 3 = dov = [(ia" )(eb )](No. M+)
dov = 1 implies that d > 128.
No. 10 = dz = [(ea )(eb )](No. ^3)
No. 7 = dz" = [(ea" ) v/ (eb )] v (No. i+U)
dz = 1 implies that d < 129.
No. 12 = (d < 61+) = [(ea ) v (eb )](No, 15)(No. U0 v [ )ea )(eb )](No. U3)
(d > 0) = d (No. 11) v (No. 10)
When gED = 1, many of the decoder outputs defined above are gated into
the corresponding Felements of the ED register. For example, No. 8 = dov is
gated into the ESOV Felement when gED = gES v DgE = 1. If the true output
("1" side) of these Felements has unit value (positive voltage) following this
gating operation, then the condition indicated by the Felement name is true with
respect to the contents of ES or E depending on whether gES or DgE was performed.
The conditions indicated by the ED register refer to the ES register only because
gES is used a little more frequently than DgE. When gED = 1 because DgE = 1,
these conditions should all read E = 1, E = 3, etc., instead of ES = 1,
ES = 3, etc.
132
Fifth Row
This row consists primarily of Felements and cable drivers. One
exception is the logic used to form the input to the EDC Felement.
EDC = (es = k)(es = 0)(es = l)(es = 2)
This signal is gated into EDC when gEA =1. As explained earlier, the true
output of EDC, edc, is used only to control the transition between slow and fast
modes of shifting in the A9 step of the floating add sequence.
The dov and dz signals deserve special attention. Since the exponent
adder operates modulo 256 with the most significant bit position assigned a
■7
weight of 2 , its output, d, may be overflowed in the positive direction (dov = l)
even though d appears negative (i.e., cL = l) and conversely. Let d = ea + eb + c
where c = 1 or depending on whether C is true or not. In the following case
analysis, C will be assumed true or false as required to establish the limits.
(A) If < ea < 127 and < eb < 63, then
< d < 127 or 128 < d < 65.
(B) If < ea < 127 and < eb < 127, then
< d < 127 or 128 < d < 1.
Note that in both cases the sum overflowed when d fell in a negative range.
To detect these cases, the decoder must note that ea and eb are both positive
and d is negative. Hence, dov = (ea )(eb )(d ) which agrees with the equation
given above .
(C) If 128 < ea < and 6k < eb < 0, then
128 < d < or 6k < d < 127.
(D) If 128 < ea < and 128 < eb < 0, then
128 < d < or < d < 127.
In these two cases the sum is underflowed (i.e., overflowed in the negative dir
ection) when d falls in a positive range. When d is underflowed, the sum
133
represented by the fractional and exponential parts is considered zero. It is
clear that dz must have unit value when ea and eh are both negative and d is pos
itive. Thus, dz = (ea 7 )(eb r ) (d_) which agrees with the equation given above.
Note that neither dov nor dz can be true if ea and eb disagree in sign regard
less of how C is set.
Similar considerations must be taken into account when analyzing the
formation of the (d < 6k) and (d > 0) signals. These considerations were over
looked in the original design. This was pointed out by R. H. Farrell and sub
sequently corrected as shown above.
One additional comment concerning the timing of the gES and DgE gates
is in order at this point. When the exponent adder is being used as a counter
to control the number of steps performed in the add, shift, multiply, or divide
loops, the flow of information through the adder and decoder may be described
as follows. If the inputs to the exponent adder are changed either by gating
a new word into EA or by changing the setting of the sD selector, some time must
elapse before the adder output is reliable. Additional time is needed before
the decoder outputs are reliable. Therefore, the adder output, d, could be
gated into ES or E via gES or DgE before the decoder outputs are reliable at
the inputs to the ED register. However, since gED = gES ^ DgE, it is neces
sary to insure that gES or DgE remains on long enough for the decoder output
to become reliable and set the ED Felements accordingly.
13U
h. THE LINK MECHANISMS
The Link Mechanisms (LM) include gates, selector mechanisms, and con
trol status memory elements. Delayed Control (DC) directs the data flow and
processing in the Arithmetic Unit (AU) via the LM. DC requests may determine
the state of the LM directly or indirectly through the outputs of decoders. The
inputs to these decoders may be the outputs of registers, adders, or status mem
ory elements. Selector mechanism and status memory elements remember their pres
ent state. The outputs of certain status memory elements influence the branch
ing of DC. The setting of one or more of these elements during the present con
trol step partially determines the sequence of future control steps.
If the design of DC were completely speedindependent, each request
would be answered with a reply of the same parity indicating the action request
ed has been completed. The goal of speedindependence was only partially real
ized. With few exceptions, a direct or indirect request to a link mechanism is
answered with a reply of the same parity which indicates that at least part of the
link mechanism logic has responded. This reply does not indicate completion of
the resulting change in state of the AU and/or control path. DC also sends by
pass requests to certain LM to obtain a reply without changing the LM output.
In terms of physical location, the LM occupy a central position in the
Arithmetic Subsystem. They collect requests from DC and send their outputs to
the AU and their replies back to DC. The gates and selector mechanisms are lo
cated in the Q, A, and S elevels of bays 6c, TC, 8C, l6FC, and l6RC. The con
trol status memory elements are primarily located in Q8F and Q8R. Certain spec
ialized status memory elements such as EXA, EXF, and EXR are located with the
associated control area logic.
To facilitate the collection of requests and the distribution of re
plies, four request areas (generally covering one A level chassis) and thirteen
reply areas were established during layout of DC. The requests from various
135
control areas are fed to secondary AND's (actually A s followed "by inverting cable
drivers) located in one of the four request areas. The outputs of these second
ary AND's then feed a primary AND next to the prime driver(s) or the inputs of
the link mechanism being considered. The reply signal is distributed by one to
three cable drivers to NOT circuits located in the various reply areas. The reply
— *
signals at the output of these NOT's then feed the A 's and OR's in the appro
priate control areas .
The four request areas are: RQ1 located in the A9F chassis, RQ2 lo
cated in A15F, RQ3 located in A15R and part of AlUR, and RQU located in A10R.
The thirteen reply areas are: RP11 in Q9F; RP12 in S9F; RP21 in Q17 and Ql6F;
RP22 in Sl6F and S15F; RP23 in A15F and Ql6F; EP2h in A17, Al6R, S17, and Sl6R;
RP31 in Ql6R and Q15R; RP32 in Sl^R and SlUR; RP33 in AlUR and QlUR; RPU1 in Q9R
and Q10R; RP1+2 in S10R and S11R; RP^3 in A11R and Q11R; and EPkk in A9R and S9R.
Request and reply references are shown in the input and output tables
at the left and bottom of the LM drawings. Unfortunately, these tables differ
from those appearing on AU and DC drawings. A key for the information contained
in these tables appears in the upper and lower lefthand corners of all LM draw
ings. For additional information regarding the layout of the LM and the asso
ciated logic, see File No. 528, "A Description of the Logic Drawings for the Arith
metic Subsystem" by J. 0. Penhollow.
A word of caution is in order concerning the signal notation for re
quests, replies, and outputs of LM. Negative logic notation is used in DC and
positive logic notation is used in the AU. For example, DIOa or gAU (DII87)
will turn gA "on" when they have a negative voltage level, i.e., DIOa = or
gAU = 0. The gA outputs shown at the top of the drawing are "on" when they
have a positive voltage, i.e., when gA = 1. If gA = 1, the outputs of the sA
selector as described in section 3.1.2.6 are allowed to set the A register F
elements. In response to a "0" request by DIOa or gAU, a "0" reply such as
gArc or gArcla is returned to DC. When all of the LM requested by a given
1 ^c
control area have returned "0" replies, the control area responds by sending out
a "1" request signal which turns off gates (so that gA = 0) and places the selec
tor mechanisms and status memory elements in a memory state, i.e., allows them
to retain the state to which they were set by the "0" request. The LM replies
respond to a "1" request by returning a "1" to DC which conditions the next control
area. Although a gate was used as a specific example, similar statements apply to
the requests, replies, and outputs of selector mechanisms and status memory elements
In the next three sections the logical operations of a sample gate, se
lector mechanism and control status memory element are discussed. Special LM are
also considered.
^.1 Gates
There are seven regular gate logic drawings: gA (DII87), gQ (D1188),
gS (DII89), gR (D1190), gEA (D1193), gE (D1195), and ESgEM (D1500). The op
eration of gQ is discussed as an example.
Assume that gQ is off initially such that all request inputs at the
left side of the drawing are "1", all replies (i.e., NOT outputs) at the bottom
of the drawing are "1", and all gQ outputs at the top of the drawing are "0".
Assume that an MPY order is being executed and control area M3 (D128l) has just
become active. The M3a output goes from "1" to "0". This request is fed to the
secondary AND cable driver in RQ2 (Al6F) . Its output, gQ2, goes from "1" to "0"
and feeds the primary AND in the A8C chassis. The output of this AND, RQgQ also
goes from "1" to "0". This causes gQ to go from "0" to "1" at the gate inputs of
the F elements in the Q register. Under slow reply conditions, the change from "1"
to "0" at the otuput of the D 2 in Q5C is fed to the INHIBIT AND OR in A8c causing
the output of this element to go from "1" to "0" provided the MSAQ inhibit signal
from the console is "1". The "0" output of the INHIBITAND0R feeds three invert
ing cable drivers and a collector follower. The cable drivers feed seven NOT cir
cuits in various reply areas. In particular, the gQRbla reply goes from "1" to
■137
— *
"0" and feeds the A and OR circuit associated with control area MU (D128l).
When all reply inputs to the two OR's in M^ are "0", the output of the
second OR causes the EcclesJordan in M3 to set to a "0" so that the associated
M3a output changes from "0" to "1". By following this "1" through the gQ logic,
it is easily seen that gQ goes from "1" to "0", thus closing the gate to the Q
register while the replies including gQrbla go from "0" to "1". When all of the
)f
reply inputs to the A in Mk are "1" its output goes to "0" since the Mk Eccles
Jordan was set to "l" while M3a was "0". This represents the beginning of the
next control step in the multiply sequence.
Under fast reply conditions, the gQr input to the INRTBITAND0R is
disconnected and the output of the primary AND, RQgQ, is connected in its place.
This eliminates five collector delays in the feedback loop but sacrifices a check
2
on the prime gate driver and one of the D drivers. Note that the exponent gate
logic always operates under fast reply conditions.
The MSAQ inhibit input is controlled from the console and is used dur
ing stepbystep sequencing of DC. As long as MSAQ = 1, the gQ replies are al
lowed to go from "1" to "0" in the normal manner. If MSAQ = 0, the gQ replies are
held on a "1" until the operator removes the inhibit causing MSAQ = 1. When a
control area requests gQ and MSAQ = 0, the Q register Felement gates are held
open. Likewise, any other LM requested by this control area are held in the ac
tive state. The EcclesJordan associated with the control area cannot be set to
y
"0" and thus allow the A. to produce a "1" request until the gQ reply is allowed
to change from "1" to "0" . For additional information concerning inhibit sig
nals, see File No. U09, "Manually Stepping Through DC" by R. E. Swartwout.
In certain control steps gQ is done conditionally. The logical struc
ture of DC is such that a reply from the gQ logic is needed in these cases
whether the gate is performed or not. A bypass gQ request is used to obtain
the reply when the gate is not performed. Note that if either By gQ2 or By gQ*+
go from "1" to "0", the gQ replies (such as gQrala, etc.) go from "1" to "0"
138
but gQ at the inputs to the Q register Felements remains "0" .
In the remainder of this section, we consider four gate logics which
have some irregularites and six special gates which do not appear on separate
drawings .
The DgE and gES drawings show an output to EDM (DI50U). When either
DgE or gES is requested, the gED gate shown on EDM is also requested. Note
that gED = gES ^ DgE as discussed in section 2.2.U.
The 6UgES gate logic also appears on gES (DII9A). Since this signal
feeds the clear inputs of the ES register Felements, it is active when 6UgES
is "0". Therefore, a LEVEL RESTORER appears in place of a NOT on QJR. A "0"
request for 6^gES produces a "0" gES reply in DC as indicated by the AND ahead
of the cable drivers in A8C f
The FlgMEM and RESgOUT logic appears on FRgMF (DII9U). The former
is used only during decode (Gl) while the latter is used only during store (S9).
The collection of requests and the distribution of replies is limited according
ly. The primary gate drivers are located in the Gl (D1276) and S9 (D128U) con
trol areas.
The R • MgM and R v MgM gate logic is shown on RgM (DII91). If both
R • MgM and R ^ MgM are requested similtaneously, RgM is accomplished as dis
cussed in section 3.1.2.2. During the clear add, (b), sequence, R • MgM or R ^ MgM
may be done separately. The conditional logic that decides which gate is actual
ly performed during B2 appears at the left edge of the RgM drawing. B2RgM must
be "0" before any output of this logic can assume a value other than "l".
The a„gA gate is shown on HAS (D1522). It is used to copy the con
tents of A into A during the execution of a shift instruction, a store in
struction which uses the shift, (f), sequence, or a BLS order. The black gate
symbol by the A Felement indicates that a gA is "0" when active.
The OgQ, Qi , gate logic appears on LQR (DI52U). This gate clears the
Qi „ and Q, , Felements to zero during decode (Gl) and K3 step at correct overflow,
139
(k), sequence when clearing an SSC or ASC order. The OgQ* _Qi . k signal is "0"
when active.
The m, igEM^ gate is used only during El of the exponent arithmetic, (e),
sequence. The gate driver appears in the El control area (D1270). This gate
allows eight bit exponents to "be brought into the EAU from Fl. When m. . gEM_ = 1,
the contents of M are copied into EM. This overwrites the Fl, bit that was
placed in EM^ and E1VL during Gl via FlgMEM. (See section 3.2.2.1.)
The gCB logic appears in the carryborrow section of SEC (D1527).
When gCB = 1, the output of the carryborrow logic is transferred to the CB
Felement (see section 3.1.13). As shown on SEC, this gate is only used during
the All step of the add, (AJ, sequence and the D13 step of the divide, (d), se
quence .
1
The gH gate request occurs only during the D6 control step of the di
vide, (d), sequence as shown on D1272. The gate driver and the H EcclesJordan
appear on DPa (D1507). When gH = 0, H is set to "1". This is done to in
sure proper recoding of the first quotient digit as discussed in section 3.1.17.
k.2 Selector Mechanisms
There are seven drawings of selector mechanism logic. Four selector
mechanisms are associated with the MAU: MsAI (DII76), MsSI (DII78), sAQI
(DII80), and sSRI (DII82). Their companion drawings showing the distribution
of selector gate signals to the selectors in the MAU are: MsAII (D1177)*
MsSII (D1179), sAQII (Dll8l, and sSRII (DII83).. The three selector mech
anism drawings associated with the EAU are: sD (D118^), sEA (DII85), and sE
(DII86). These drawings also show the distribution of the selector gate sig
nals.
In all cases, the selector may be viewed as an nstate EcclesJordan
•lUO
memory element where n is the number of selector options. Certain peculiarities
arise in connection with the MsS selector mechanism because the MMsS request causes
the MsS and MsS options to be turned on together. This is discussed in detail
below. The basic logic for the selector mechanisms was suggested by Professor
D. E. Muller. It was developed and modified to fit the needs of the order code
and a "speedindependent" DC by R. E. Swartwout.
Each active request ("0" input) causes the selector mechanism to re
lease its old setting and check that all selector gate signals (outputs) are "0",
and then establish and latch the new setting. These events occur sequentially to
prevent overloading the selector emitter followers at the associated register or
adder output. If the old and new selector settings were on simultaneously, the emit
ter current into these transistors would be twice the design value. After the
selector mechanism has theoretically latched in its new state, the associated
reply goes from "l" to "0". When this indication is received by the control area
following the one which initiated the selector request (i.e., the active control
area), it is mixed with other replies in an OR. When the output of this OR goes
from "1" to "0" to the EcclesJordan in the active control is set to "0", causing
— x
the request at the A output to change from "0" to "1". This returns the active
input to the selector mechanism to "l" and leaves the state of the selector un
changed, but causes the reply to go from "0" to "l". When all activated link
y
mechanisms are relaxed such that their replies are "l", the output of the A in
the following control area goes from "l" to "0" which initiates the next control
step.
The method of collecting requests and distributing replies is similar
to the one described for the gates. It should be noted that many of the selector
— *
requests are made by decoders which are conditioned by 'certain control area A 's.
Examples of these are the U and 6 decoders and the division predictors shown on
u9D (DI506) and DB2 (DI507). The use of bypass requests and console inhibit
■lUl
signals is the same as described for the gates. Connections for fast and slow
replies also exist for the selector mechanisms associated with the MAU. As
for the gates, the shorter reply time is achieved by eliminating the prime dri
—2
ver, a D driver, and a return cable driver from the reply chain. The fast
reply connections are indicated by dotted lines on sAQI (Dll8o) and sSRI
(DII82). The replies for the EAU selector mechanisms are all fast in this
sense.
As an example of how the selector mechanisms operate, consider MsA
(DII76). Assume MsA is set to OMsA initially, meaning that the b outputs of
the MsA selector in the MAU are all "0". Let MSAQ, = 1 (i.e., the console inhi
bit switch is "off"). Furthermore, assume the inputs to the restoring AND's
shown down the center of the drawing are all "l", and the replies at the outputs
of the NOT's across the bottom of the drawing are also all "1". It follows that
RQ2MsA = RQMsA = RQOMsA = RQMsA = RQKgA = RQMsAa = RQMsAb =1. At the
top of the drawing, 2MsA = MsA = MsA = KgA = 2MsAr = MsAr = MsAr = KgAr = OMsA =
OMsAr = 0, while OMsA = KI = 1. At the right side of the drawing, we have
RP2MsA = RPMsA = RPOMsA = RPMsA = RPKgA = 1, If DlUByMsA = ByMsAU = 1
(i.e., these bypass requests are not active), then MsAra = MsArb = 0, The
direct reply to M6 and Dll, MsArb, and the NOT outputs are all "l". At the
bottom of the selector mechanism logic, KgA = ca = and KgA = 1. The destina
tions of these outputs as well as the reply, MsArb, are shown in the "Direct
Connection" boxes at the bottom of the drawing.
Under the above conditions, the selector gate signals denoted by
2MsA, MsA, MsA, and KgA are held to "0" by the OMsAr which is also "0". Note
that OMsAr feeds each of the four nonrestoring AND's which appear in a line down
the center of the MsAI drawing.
Now suppose that one of the following MsA request inputs goes from "l"
to "0": MsAul, MsA.u2, MsA0, MsAp, or DlUMsA. The source of these requests
lU2
is indicated by the input table. RQMsA goes to "0" which in turn causes RQMsAb
to go to "0". RPMsA remains a "1" momentarily since MsAr is still "1" at this
point. 2MsA, MsA, MsA, and KgA remain at "0" and KI remains at "1" because
OMsAr is still "0". RQMsAb going to "0" changes OMsA from "1" to "0" and
causes OMsA = OMsAr to change from "0" to "1". The old setting has been re
leased at this point. Note that RPOMsA and all other such signals are still
"1". When OMsAr goes to "l", 2MsA, MsA, and KgA remain at "0" and KI remains
at "1" since RQMsA = RQMsAb = 0. However, MsA goes from "0" to "l". As
shown on MsAII (D1177), MsAr also goes from "0" to "l" causing the MsAr NOT
output on MsAI (DII76) to go from "1" to "0". Since RPMsA is still "0",
RPMsA also goes from "1" to "0" and causes all of the replies to change like
wise. At the same time, the "0" MsAr signal is fed back to the nonrestoring
AND's whose outputs are RQMsAb and KgA. This is the latch signal which holds
the MsA selector setting when RQMsA goes back to "1". The latter change occurs
when the "0" reply in conjunction with "0" replies from other active link mech
anisms causes the request from the active control area to change from "0" to
"1". When this causes RQMsA to go from "0" to "1", RPMsA changes from "0" to
"1" and causes all the reply outputs to follow. This completes the active cycle
of the selector mechanism.
If the next request to the MsA mechanism is also for MsA, the MsA
reply changes from "l" to "0" much faster. Since MsAr = 0, RPMsA changes to
"0" as soon as RQMsA does. This is simply a consequence of the fact that the
selector mechanism is already in the state requested. If the next request is
not MsA, a process similar to the one described above will yield the new set
ting.
It is worthwhile to note that MsA and ca have the same parity. The ca
signal is the carry input in the hk — position of the A adder as shown on LAS
(D1523) and LAD (D1212). In complement arithmetic, the subtraction of M from A
1U3
is accomplished by adding M (bitwise complement) to A with a carry in the least
significant position. Therefore, M is subtracted from A when MsA = ca = 1.
(See section 3.1.5.)
The delay shown in the RPKgA output line is necessary to insure that
the assimilated value of A appears at the Aadder output before starting the
next control step. This is especially important if the next step involves a
control branch which is conditioned on the alogic outputs shown on DPCC (D1507),
and discussed in section 3.1.9. An example of this is the Kl control step shown
on D1279. Since KgA is usually requested by the same control area that requests
gA, the time required for the Aadder outputs to become reliable is quite long.
The A register must set to its new value feed the carry generator which in turn
must feed the A adder. There is no way of knowing when the A adder outputs are
reliable so the reply must be sufficiently slow to cover the worst case con
dition.
Because of its location, the delay in the RPKgA output line only needs
to be half of the total delay required under worst case conditions. When KgA
is requested, the "l""0" and "0""l" changes on RPKgA are both delayed by the
amount specified even though KgA may have been set previously. A delay is neces
sary under the latter condition because all of the stored carries gated into A
at the time of the second KgA request are "0". This change in A must flush
through the carry generator and A adder before the output of the latter is re
liable. When the second request is for any other setting of the MsA mechanism,
the reply time is not influenced by the KgA delay. Furthermore, this delay does
not slow down the KgA latchback signal, KgAr.
The KgA and KI signals shown at the top of DII76 are logical comple
ments. When KgA = 1, the nonstored carry outputs of the A adder represent the
assimilated value of the A register. The stored carry outputs, <X , would be
ikk
equal to the evennumbered b. if allowed to operate normally. Since these car
ries have already been taken into account by the adder, the KI = signal is
used to inhibit them. Therefore, a. = for all i when KgA = 1.
The MsS selector mechanism logic (D1178) is complicated by the need
to set MsS and MsS simultaneously with cs = when MMsS is requested. This
causes a field of units to be added to the contents of the S register which
amounts to subtracting a unit in the hk — position. The NOT order which does
a bitwise complement of the operand in M requires that MsS be set with cs = 0.
Furthermore, the SUB, SSC, CSB, CST, STN, MPY and all divide orders use either
MsS or 2MsS with cs = 1. During the terminal steps of a case h addition and dur
ing quotient roundoff, it is convenient to allow cs = 1 with OMsS = 1, This
corresponds to the CS request which adds a unit in the UU — position.
The speedindependent realization of the MsS selector mechanism uses
two EcclesJbrdans called MO and CS. There is no restriction on the order of
the requests except a CS or MMsS request must always be followed by the clear
request, KMsS. The latter returns the mechanism to the OMsS state and insures
that MsS and MsS selector gate signals are both "0".
There are four selector replies: MsSr, MMr, CSr, and KMsSr. The
MsSr signal corresponds to MsAr and is used most frequently. The remaining
replies are used in pairs. When 2MsS; MsS; OMsS; M; CS; MsS; or 2MsS is re
quested, MsSr changes from "l" to "0" while MMr, CSr, and KMsSr all remain at
"1". If CS is requested, only CSr changes from "l" to "0". If MMsS is re
quested, only MMr and CSr go from "l" to "0". When KMsS is requested, only
KMsSr and CSr go from "l" to "0". The ByMsS, ByMM, and ByCS requests also
cause the corresponding replies to change from "1" to "0". There is no con
sole inhibit associated with MMr, CSr, or KMsSr.
The MO memory element has a reply output and is normally in the "1"
.1*5
state. It is set to "0" only when MMsS is requested. The CS memory element is
set to "0" except after a MsS, 2MsS, or CS request.
As an example of how the MO and CS memory elements function, consider
an MMsS request followed by KMsS. As in the MsA example, assume the mechanism
is initially set to OMsS and all requests and replies are "1". MO is set to
"1" (i.e., mo = l) and CS is set to "0".
An active MMsS request causes RQMMsS to change from "1" to "0". This
in turn changes RQKMMsS from "l" to "0" which yields CSr = since cs = ini
tially. At the same time, MO is set to "0" such that mo = and MOr = 0.
Since mo goes to "1" before MOr goes to "0", KMsSr remains at "1". The output
of the nonrestoring OR which has RQMMsS and mo as inputs (appearing a little
left of center on DII78) now changes from "l" to "0". The output of the non
restoring AND which it feeds changes in a like manner and causes OMsS to go
from "1" to "0" while OMsSr goes from "0" to "l". The latter output feeds the
nonrestoring AND directly to its left and causes its output to change from "0"
to "1". This AND output then causes both MsS and MsS to change from "0" to "l"
since mo = 1. The resulting replies  MsSr and MsSr  go from "1" to "0".
This does not change RP2MsS; RP2MsS; RPOMsS; RPMsS; RPMsS; RPMsS, CS; or
KMsSr which have remained at "l" during the preceding action. However,
MsSr = MsSr = MOr = mo = causes MMr to go from "l" to "0". The "0" MsSr and
MsSr signals also feed the nonrestoring AND having (mo) ^ (RQMMsS) as an in
put. This latches the MMsS state. When RQMMsS goes from "0" to "l", CSr changes
from "0" to "1". Furthermore, MOr returns to "1" causing MMr to follow.
KMsS must be the next request. Incidentally, this request is used
when DC is cleared. When RQKMsS goes to "0", RQKMMsS also goes to "0" and sets
CS to "0". (The latter operation is necessary in case CS was the previous re
quest.) This yields CSr = 0. At the same time, RQKMsS causes MsS and MsS to
change to "0", and holds 2MsS and 2MsS on "0" while MsSr and MsSr change from
1U6
"0" to "1". The latter changes permit OMsS to go to "1" with OMsSr changing to
"0", thus latching the new state. Since OMsSr = RQKMsS = 0, MO is now set to
"1" such that mo = MOr = 0. This causes KMsSr to change from "1" to "0". When
RQKMsS returns to "1", RQKMMsS and CSr go to "l". Furthermore, RQMO goes
to "1" which causes MOr and KMsSr to change from "0" to "1". The mechanism is
left in the OMsS state  meaning that the t. outputs of the MsS selector in
the MAU are all zero.
In the sAQ, or sSR mechanisms a state may correspond to different set
tings for the associated A and Q or S and R selectors. In all cases, the gate
signals are defined for sA and sQ, or sS and sR selectors in the MAU. For example,
the sSR mechanism shown on D1182 has a state called OAsSR. In this state, the
sS and sR selectors in the MAU are set to OsS and AsR respectively. When
gS = gR = 1, zeros are placed in the S register and the output of the A adder,
OL, is placed in the R register.
The sD mechanism (D118U) is similar to the MsA and MsS mechanisms
except that an EMsD request does not cause a complement carry to be added to the
least significant position of the exponent adder. This request sets the sD
mechanism to the EMsD state which insures that eb . = em. as shown on EAU (D1502).
11
If the contents of EM are to be subtracted from the contents of EA, EMsD and C
are set to "l". The true output of C (DI285) represents the complement carry
into the — position of the exponent adder as discussed in section 3.2.3.
Many of the states in sD, sE, and sEA represent constants at the out
puts of their associated selectors. For example, 2sD produces eb. =0 for
st
i = and 2 < i < 7 while eb. = 1. Since the 1 — bit position in the EAU has
a weight of 2, the effect of this selector setting is to add 2 to the contents
of EA. As a second example, 6sE causes the 1 — and 2 — inputs to the E register
to be "1" while all others are "0". Thus, when the sE mechanism is in this
state and gE is perform, the E register is set to 6.
li+7
U.3 Control Status Memory Elements
The control status memory elements are EcclesJordans with reply out
puts. The circuit schematic and logical structure of this element is shown on
drawings B95^ and DU36. If EJ is a control status memory element, the re
quest inputs to the "l" and "0" sides are called EJ and EJ respectively. The
reply is called EJr. The outputs from the "1" and "0" sides are called ej and
ej respectively. In the memory state, EJ = EJ = 1 such that ej and ej retain
their previous values while EJr = 1
Assume that ej = 1 and ej = 0. If EJ now goes to "0" while EJ = 1,
ej changes to "l" while ej and EJr remain at "1". After EJ = and ej = 1, ej
goes to "0" causing EJr to change from "1" to "0" since EJr = (EJ v eJ)(EJ ^ ej).
The "0" reply indicates the memory element has been set to the new state and theo
retically latched. When EJ goes back to "1" with the EJ input remaining at
"1", the new state is retained and EJr goes to "1". This completes an active
cycle for the EcclesJordan with reply. As in the case of selector mechanisms,
the EJ reply goes to "0" much faster when the EcclesJordan is already in the
state requested.
The method of collecting requests and distributing replies and out
puts is similar to that described for gate and selector mechanisms. As opposed
to the other types of link mechanisms, some control status memory element out
puts feed logic in both the AU and DC. By feeding the reply output to an AND,
bypass requests are possible. These requests enter the AND, causing its out
put to change from "l" to "0" to "l" without changing the state of the memory
element .
All except one of the control status memory elements (these do not
include DCRFL, INFL, and DCRS) are set to both "0" and "l" by DC. The excep
tion is 0V (D1291) which is set to "l" by DC but is reset to "0" (i.e., cleared)
ll+8
by AC. OV is also the only status memory element whose reply may "be inhibited
from the console. This is accomplished by making MSOV = 0.
A brief description of the function of each control status memory
element follows .
The C status memory element appears on D1285. It is conditionally
set to "0" or "1" during Gl (D1277). During the execution of DC orders, it is
set to "1" whenever a carry into the least significant position of the exponent
adder is needed. The c output represents this carry as shown on EAU (D1502)
and discussed in section 3.2.3. The c and c signals are also used as inputs to
the conditional logic of the K2 (D1279) and R2 (D1282) control areas.
CL and CR shown on D1286 are used during the circular left and right
shift operations for case 3 addition as discussed in sections 3.1.12 and 5.5.
CL is set to "1" during A9 (DI269) to condition the paths a > R. , a * R, ,
and a ~* Qlo> a n * \h' It i s se t to "0" during All. Likewise, CR is set to
"1" during A10 (DI269), to condition the paths a * S , a * S and
a_n  A_ x , a _ 2  A . CR is set to "0" during Gl (D1276_, Kl, or K3 (D1279).
The cr and cr outputs are also used as inputs to the conditional logic of A9
and A10. To increase the speed of the add loop (A9 and A10) bypass logic for
the CL and CR replies is also provided.
The DL memory element shown on DI287 is set to "l" to condition the
paths V > Si , v„ > Si 1 and p >■ A. , p > A, , . DL is conditionally set to
"0" or "1" during Gl ( D1277) as well as D3 and DIG. It is always set to "1"
during A13, D6, and F3, and is always set to "0" during A6 and Dl6. The dl and
dl outputs also feed the conditional logic in the A9, All, D5, Dll, Fl, F2, F8,
Kl, K2, Rl and R2 control areas. In many cases, dl and dl determine whether gQ
and gR are performed or bypassed. If dl = 1 (i.e., if DL is true), a double
length left shift in S,R and A,Q is possible, so gS,gR and gA, gQ are used. If
1U9
dl = 0, only a single length left shift is S and A is possible, so gS, By gR
and gA, By gQ are used.
The EXA, EXF, and EXR status memory elements shown on D1288 control
the exit from the inner loops of the '(A), (f), and (r) sequences respectively.
The exa and exa signals feed the A s of All and A9 (D1269) respectively.
The A s of F3 and Fl (D127^) have exf and exf as inputs. Likewise, exr and
exr feed the A s in R3 and Rl (D1282) respectively. Note that EXA and EXR are
set to "0" when DC is cleared. EXF is set to "0" by the Gl request which sets
the Fl Eccles Jordan to "0".
In general, the EX memory element is set to "0" or "1" prior to enter
ing the associated control loop. If ex = 1 at the time of entry, the loop is
bypassed. For example, this may occur when entering the normalize, Qt), loop.
If exr = 1, upon entry from Gl, control passes immediately to R3 and on to the
first control step in the (d), (m), (sf), or (v) sequences. If ex = at the
time of entering the loop, the first and second steps of the loop are executed.
If the conditions for setting EX to "1" arise during the first step, a request
to set EX to "1" is made by the second step (such as A10, F2, or R2), and exit
from the loop occurs on the third step since ex = 1. If the conditions for set
ting EX to "1" do not arise during the first step in the loop, control continues
to cycle through the loop until these conditions do arise on some oddnumbered
step  say 2k + 1. During the 2k + 2 step, EX is set to "l". Since ex = 1,
exit from the loop occurs during the 2k + 3 step.
As shown on DI289, the J memory element is conditionally set to
"0" or "1" during Gl (D1277) and is always set to "1" during VU (D128o). The
and j outputs feed the conditional logic associated with the Gl, Dl, Rl, SI,
S5, S9, VI and V3 control areas. These signals condition the choice of R • MgM
or R v MgM during B2 as shown on RgM (DII91). They also feed the store logic
shown on HQR (DI525) as discussed in section 3.1.2.1*+.
150
The N memory element appears on D1290. It is conditionally set to "0"
or "1" during Gl (D1277) and is unchanged during other control steps. The n and
n outputs influence the conditional logic in the Dl, Ml, Rl, SI, S5, and S10 con
trol areas. The n signal also feeds the store logic shown on HQR (D1525) and is
discussed in section 3.1.2.1U.
t
Both OV and OV appear on D129L They are used for overflow indication.
The effect of the ODIR signal on the OV request input and the OV bypass logic is
considered in section 5.1, Both OV and OV are set to "0" when DC is cleared.
OV is conditionally set to "1" or bypassed during D7, D15, E3, F2, F5,
K2, M3, and S9„ It is conditionally set to "l" during D5 and conditionally by
passed during Kl, K2, and M8. The ov output is used only by AC to detect accu
mulator overflow (both fractional and exponential). Only AC can set OV to "0"
by causing Reset OV = 0.
The OV memory element is conditionally set to "0" or "l" by the Fl
(DI27I+) control step only. It is used as a buffer storage element for OV dur
ing the inner loop of the shift, QO, sequence. Its outputs are used in F2 con
ditionally to bypass OV or set it to "l".
The RO memory element appears on D1292. RO is set to "0" when DC is
cleared. It is set to "1" whenever the fraction in A is to be rounded. In parti
cular it is set to "1" during Dl, Ml, and VI. It is conditionally set to "0" or
"1" during SI, and is always set to "0" during D3, M3, S9, and V3. The ro output
conditions the roundoff logic shown on ZDR (DI505) and discussed in section 3.1.7.
The TC memory element also appears on D1292 „ It is conditionally set
to "0" or "1" by Gl ( D1277). It is always set to "0" during Sll (D128U). Ex
cept for the CAE and CSE orders, TC is set to "1" for "storeclear" type instruc
tions (STC, ASC, or SSC). The tc and tc outputs feed the conditional logic in
the K2, SI, and S10 control areas.
As shown on D1293, "the X memory element is conditionally set to "0"
'or "1" by Gl (D1277). It is always set to "l" during DU (D1271) and to "0"
151
during S6 (D1283). The x and x outputs feed the conditional logic in the Dl, D2,
D3, SI, andS5 control areas. They also affect the logic between the low ends of
R and FO as shown on LQR (D 152*0 and discussed in section 3.1.2.1^.
The Z memory element is shown on D129^. It is set to "l" when the
fraction in AQ becomes zero or when the exponent becomes less than 128. It is
also set to "1" in DT (D1272) if ZA is set to "l" (i.e., za = l) during (R) as
as consequence of A containing zero. Z is set to "0" by any instruction which
uses the Qb) sequence and by the LAL instruction. The z and z outputs feed the
conditional logic associated with the Al, A2, A3, D5, D6, Fl, Kl, K2, Ml, M3, Rl,
S5, S7, and S9 control areas. The z output also goes to AC.
The ZA, V, and ZV status memory elements appear on D1295. All three of
these serve very special purposes. Note that V and A are cleared to "0" by cdc.
ZA is always set to "0" during Gl (DI276). It may be set either to "0"
or "1" during R2 (DI282). The latter setting occurs only when a single length
normalization is being performed and A is found to contain zero. (A single length
normalization is used only when Rl is entered from DU of the divide sequence.)
The za and za outputs feed the conditional logic in D5, D7, and Rl.
The V memory element is set to "l" during D13, S2, and also during SI
if tc = 1. It is set to "0" during D17, Sll, and also during SI if tc = 1. If
tc = 1 and XCH is not being executed, V is also set to "0" during S10. The c!
and B outputs influence the formation of the a and a signals as discussed
in section 3.1.2.6 and shown on HAS (D1522). The <$ output is used to close the
paths a, + R and a, , * R during S2 (D128U). This latter use is mentioned
in section 3.1.2.12 and is shown on HQR (DI525).
The A memory element is set to "l" by the request from D10 ( D1272)
and reset to "0" by the request from DlU (D1273). The (6 a) output allows
(3, to feed the input to R> p during the inner loop of the (D) sequence. This is
discussed in section 3.1.17 and appears on LQR (DI52U). The (6 b) output modi
fies the function performed by the carryborrow logic (DI527) during division
152
as discussed in section 3.1.13.
6, appears on D1296. It is conditionally set to "0" or "1" during Gl
(D1277) and V3 (D1280). It is always set to "1" during P£ (D1268). I
and 0. outputs are inputs to the conditional logic associated with the Dl, D2,
D3, D5, Ml, PI, Rl, S10, and VU control areas. They also feed the Q decoder as
shown on [xQD (DI506) and discussed in section 3.1.1^.
6 is shown on D1297. It is conditionally set to "0" or "1" during Gl
(D1277). Its state is never changed during the execution of an instruction. The
9 and 9 outputs feed conditional logic in the B3, Dl, D2, D3, D5, Ml, PI, Rl, SI,
and S10 control areas. These signals also feed the 0decoder as shown on U0D
(DI506), and condition the choice of R • MgM or R v MgM during B2 as shown on
RgM (D1191).
The A memory element appears on D1298. It is conditionally set to "0"
or "l" during Gl (D1277) and is not affected by other control steps. The \ and
\ signals are inputs to the conditional logic in the Bl, B2, B3, Fl, F2, Fk, F5,
SI, S5, S7, and S9 control areas. The \ output also feeds the end connection
logic shown on HAS (D1522) and discussed in section 3.1.2.8.
The [X and Q, memory elements are shown on D1299. These elements play
very special roles. The former is used only during the \W) sequence while the
latter is used only during the '" A) and (fJ sequences. They are Tooth set to "0"
when DC is cleared.
In Ml (D1281) u is always set to "1". It is likewise set to "1" dur
ing M6 until the final pass through the multiply loop during which u is set to "0" .
The [x output controls the input paths to Q. p and R, during the multiply loop
(M5 and M6). This is discussed in section 3.I.I5 and appears on LQR (DI52U).
The Q memory element is conditionally set to "0" or "1" during A9
(D1269) and Fl (D127U). The Q and Q outputs are inputs to the conditional
logic of the A10 and F2 control areas as discussed in sections 5.5 and 5.8.
■153
5. DELAYED CONTROL
Delayed Control (DC) obeys the orders it receives from Advanced Con
trol (AC) by executing a partially ordered sequence of microoperations in the
Arithmetic Unit (AU)via the Link Mechanisms (LM). The AU and LM are discussed
in the preceding sections. Each of the three types of microoperations is asso
ciated with one of the three types of LM. The microoperations are: the open
ing and closing of a register or memory element gate (such as gA), the setting
of a selector mechanism (such as UAQsSR), and the setting of a control status
memory element (such as DL or DL). A set of microoperations is called a con
trol step and is represented by a box on the DC Flow Chart. The time ordering
of the microoperations within a control step is not important so long as all
memory elements (including selector mechanisms) which may change as a conse
quence of these operations are allowed to achieve their ultimate state before
the active phase of the step is terminated. In particular, this means the
Felement gate must remain on long enough for the input logic to settle and
set the Felement.
An ordered sequence of control steps is called a control sequence.
As shown on the DC Flow Chart, there are thirteen control sequences ranging
from one control step for decode to twenty control steps for divide. The
names and abbreviations of these sequences are listed below.
15^
Floating Point Add  (a)
Clear Add  (b)
Divide  (d)
Exponent Arithmetic  Qn
Shift _______________ (y)
Decode  ^q)
Correct Overflow and Detect Zero  m
Load Q  (l)
Multiply  (m)
Store Preliminaries  M?)
Normalize  (R
Store  (s)
Difference Absolute Value  (v)
Two or more control sequences are used during the execution of every
DC order. Each order begins with the Co) sequence, continues with a series of
one or more other sequences, and terminates with the next entry to iGJ . Except
for the [EJ sequence and the premature exits from (DJ and (M) , all order sequences
must pass through one or more steps of the Ck) sequence before terminating with
an entry to (cf) . The [K) sequence detects and conditionally modifies the state
of the fractional and exponent accumulator (AQ and E) before starting the next
instruction. In particular, modulo 2 fractional overflow in AQ is detected and
corrected by a right shift of one base k position. If the compensating exponent
■155'
correction causes e > 127, then OV is set to indicate accumulator overflow. If
Z is not already set, the (k) sequence checks for a zero fraction in AQ. If so,
it sets Z. The [Ej sequence and the premature exits from Qa) and (d) skip (K)
and terminate in (G ■) directly. In each case the state of the accumulator is
determined and reflected in the settings of OV and Z before the exit to fGM is
made.
The control sequence series used to execute every DC order are listed
below. In each series, the terminal (g) represents the decode step of the next
order. The control step from which a premature exit occurs is indicated. A
dotted line means that the exit is conditional while a solid line means it is
unconditional. The three conditional exits from (k) to \Qj are not indicated.
No attempt is made to distinguish the various control paths through \Sj.
Table I: Control Sequence Series for DC Orders
Octal Code Order Mnemonic Sequence Series
00 CSB
01 CST
02 CAD
03 CAT ©^ © — * ® — *" ©
0^ NOT
05 AND
06 LOR
07 BLS
*®^©
^ Premature exit for
10 SUB
12 ADD ' ~>® " J ^~ case  1 addition
Al
Ik SSC
16 ASC
Al ! >./cS ^ Premature exit for
'>®
case 1 addition
•156
Table I: Control Sequence Series for DC Orders (Continued)
Octal Code
Order Mnemonic
Sequence Series
11
13
15
IT
SBE
ADE
CSE
CAE
@ ^©^0
20
MPY
©^©*®^®^©
Premature exit
•when multiplier
is zero or the
multiplicand
exponent is 6k
M8
1
i
.j
21
DIV
Return to [R
if the divisor
is not normal
ized
i
i n
i i
Dh i 
i i
Premature exit
when the divisor
is zero
V
D5
D8
s)
Premature exit when
the divisor is nonzero
"but the dividend is
zero
22
NDV
Unconditional
return to [Rj
with immediate
bypass to Dl if
the divisor is
normalized
1
»
*J
Bh
D5
© » ® > ©
D8
s section
^ 5.13
•157
Table I: Control Sequence Series for DC Orders (Continued)
Octal Code
23
Order Mnemonic
VID
Sequence Series
Unconditional
return to (R)
with immediate
bypass to Dl if
the dividend is
normalized
M/
V
DU
D5
©^®*@
D8
I
i/ See
G) section
i
J <r
5.13
25
XCH
D^®^©^©
2h
26
27
STR
STC
STW
K — > G
30
31
32
33
STF
SIF
SEQ
SIA
©^®^®^©^®^©
3^
35
36
37
Uo
STU
SAM
SAL
SEX
© — ®^©
Illegal
Ul
LAL
©^©^©^(g
158
Table I: Control Sequence Series for DC Orders (Continued)
Octal Code Order Mnemonic Sequence Series
k2 DAV © — ^ ® ^ ® — > ® — ^ ® —'
ai ;
Premature exit
for case 1
addition
U3 SRM ® — > ® — > ® — >
hk Illegal
h6 Illegal
k$ LRS
1+7 SRS © — > ^ (k) — > ©
The logic of DC is "based primarily on the concepts of asynchronous
circuit theory as developed "by D. E. Muller and ¥. S. Bartky. As as conse
quence of economy and the desire for speed, the physical realization of DC does
not fall within the class of speedindependent circuits unless some unrealistic
assumptions are made concerning the generation and distribution of status sig
nals such as link mechanism replies. For a discussion of logic used to realize
DC and its departure from speedindependence, see Report 130, "Further Studies
in SpeedIndependent Logic for a Control" by R. E. Swartwout .
It is difficult to talk about the departure from speedindependence
Report 75, 'A Theory of Asynchronous Circuits I" by D. E. Muller and
W. S. Bartky.
Report 78, "Theory of Asynchronous Circuits II" by D. E, Muller and
W. S. Bartky.
■159
in DC alone. A complete discussion must consider the design of the Arithmetic
Subsystem as a whole. For example, there are not provisions in the Arithmetic
Subsystem design for determining when the outputs of registers, adders, and de
coders are reliable. Furthermore, the logic of DC does not check that the out
puts of the status signal distribution systems have reached their correct state
before the control step which they govern is initiated. To guarantee that such
signals reach their correct state by the time they are needed in some future
control step, the present control step and any intermediate steps must last
longer than some minimum time. In DC the natural circuit delays and reply paths
are usually adequate in this regard. In a few cases, artificial delays have
been inserted in reply paths to insure that certain status signals are reliable
before the next control step is initiated.
The logic drawings for the DC sequences are: (AJ D1268, DI269;
® left half of D1270; © D1271, D1272, D1273; ® right half of D1270;
© D127^ and right half of D1275;© DI276, D1277, D1278; ® D1279;
© left half of D1280; ® D1281; @ left half of D1275; ® D1282;
© DI283, D1281+; and © on the right half of D1280.
The description of these sequences begins with (g) followed by (b)
and (k) to give the reader an introduction to the logical operation of DC. Ab
breviated descriptions of the remaining control sequences are then given in
the following order: ©, @, ©, ©, ©, ©, ®, ©, ®, and ® .
In correlating the description with the DC Flow Chart (D1128), the reader is
warned that negative logic is used throughout DC but positive logic expressions
appear on the chart.
A few comments are in order concerning certain symbols which appear
on the logic drawings for DC. The cdc input to every control EcclesJordan re
presents the set signal which goes to "0" when the "Clear DC" button on the
■l60
console is pressed. The symbols (Y) and QD) represent drivers for indicator
lights on the chassis and console.
The initial state of DC is established by pressing the "Clear DC"
button on the console. This sets the MsA selector mechanism to KgA and all
t
other selector mechanism to their Ostate. It clears CL, EXA, EXR, OV, OV ,
RO, Z, £k, V, fi, and u. to "0". It also sets all control EcclesJordans to
"0" except D8 which is set to "l". The net effect is to produce an active re
quest for Gl from D8, i.e., D8  Gl = 0. Gl responds to this request as des
cribed below and begins to decode the order AC has placed in DCR.
5.1 The Decode Sequence (gJ
The sequence consists of one control step, Gl, with a "latch" as
shown on GI (D1276). It uses and flushes the instruction decoder shown on
GII (D1278) and the status memory element decoder (encoder) shown on GIII
(D1277). Using the order bits in DCR the instruction decoder selects and ac
tivates (sets to "l") the EcclesJordan of the initial control step in the se
quence which follows (g). The status memory element decoder decides for each
order the setting of certain status memory elements, whether to activate gEA,
and how to set sEA and sD. The particular series of sequences which follow G
depends primarily on how certain status memory elements are set. Note that Gl
does not affect memory elements such as R0 which are turned on and off by the
sequences which use them.
The following conditions are always true at the start of the decode
(Gl) step:
(1) The result of the previous order is held in AQ, and E. For divide
orders, the quotient is held in A and E while the remainder is held in R and ES„
(2) The fraction, f, in AQ is not overflowed, i.e. 1 < f < 1.
161
(3) KgA = 1 so the assimilated value of A appears as a at the output
of the A adder.
(h) The state of the MsS selector mechanism depends on the previous
order or orders and corresponding operands.
(5) AC has previously placed the next order in DCR and set DCRFL
to "1" to indicate DCR is "full." If the order placed in DCR does not require
an initial operand, AC has set DCRS to "1" . AC may or may not have loaded Fl
(IN) and set INFL to "1" accordingly. If the order placed in DCR requires an
initial operand, then AC must have set DCRS to "0", loaded Fl (IN), and set
INFL to "1".
A summary of Gl requests as a function of the order in DCR is shown
in Table II. A "0" or "1" indicates the requested state of a status memory
element. A "l" also indicates a gate request while "0", "E", "EM", or "EM"
indicate the requested state of the sEA or sD selector mechanisms. If a check
(•/) appears, it means Gl does not request the corresponding link mechanism for
the order indicated. In the case of EXR, an "e" appears whenever the normal
ize (r) sequence follows (g) . The "e" indicates that EXR is set either to "0"
or "1" according to the state of the accumulator. In positive logic,
EXR = z(dl) v (na) v (za)(dl) v n e ? (QZ) v j(QZ). The last row of Table II
shows the first active control step after Gl.
It is important to note that FlgMEM and OgJ&«Q]i are always turned
on and off by Gl. FlgMEM allows the contents of Fl (IN) to be transferred to
M and EM in the MAU and EAU. OgQ. ^Qkk clears the two least significant bits
of the Q register to "0". Furthermore, Gl always sets DCRFL, CR, and ZA to
"0".
■l62
Table II: Gl Requests as a Function of the DC Order
h
Octal Code
00
01
02
03
ou
05
06
07
10
11
12
13
111
15
u
o
Mnemonic
CSB
CST
CAD
CAT
NOT
AND
LOR
BLS
SUB
SBE
ADD
ADE
SSC
CSE
FlgMEM
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Gate and
Selector
w
(L)
p
CO
gEA "
sEA
1
y
1
y
y
1
y
y
1
y
y
1
y
y
1
y
y
1
y
y
1
y
y
1
1
E
1
1
E
1
1
E
1
1
E
1
1
E
1
1
sD
7
y
y
y
y
y
y
y
EM
EM
EM
EM
EM
EM
DCRFL
INFL
y
w
C
7
y
y
y
y
y
y
y
1
1
0)
•p
CR
P
CO
DL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
■p
EXA
y
y
y
y
y
y
y
y
y
y
y
EXF
y
y
y
y
y
y
y
y
y
y
y
y
y
y
J>5
EXR
y
y
y
y
y
y
y
y
y
y
y
y
y
y
o
J
i
i
N
1
1
P
TC
1
1
cd
P
CO
X
1
ZA
A
1
1
1
°1
1
1
1
1
1
1
1
1
°2
1
1
1
1
1
Control
. Step Entry
<■
Bl
— >
Al
El
Al
El
Al
El
•l6 3 
Table II: Gl Requests as a Function of the DC Order (Continued)
u
CD
Octal Code
16
17
20
21
22
23
2k
25
26
27
30
31
32
33
t3
o
Mnemonic
ASC
CAE MPY
DIV
NDV
VID
STR XCH
STC
STN
STF
SIF
SEQ SIA
01
(D
FlgMEM
1
1
1
1
1
1
1
1
1
1
1
1
1
l
P
cd
TJ P
C CO
°z\ 3 %k
1
1
1
1
1
1
1
1
1
1
1
1
1
l
cd
(U o
gEA
1
1
y
y
y
y
y
y
y
y
1
1
1
l
p P
cd o
sEA
E
y
y
y
y
y
y
y
y
E
E
E
E
(D
CO
sD
EM
EM
y
y
y
y
y
y
y
y
DCRFL
INFL
y
y
y
y
y
y
C
y
y
y
y
y
y
y
y
to
CR
P
cd
DL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
CO
EXA
y
y
y
y
y
y
y
y
y
y
y
y
y
p
CD
EXF
y
y
y
y
y
y
y
y
y
y
y
y
y
y
EXR
4
y
e
e
e
e
e
e
e
e
y
y
y
y
J
i
i
i
i
8
N
l
1
1
1
1
1
0)
TC
l
1
1
CO
p
X
1
1
cd
P
CO
ZA
A
G l
1
1
1
1
1
1
1
1
1
6 2
1
1
1
1
1
1
Control
. Step Entry
Al
El
<
Rl 
— >
<
PI —
— >
■16k
Table II: Gl Requests as a Function of the DC Order (Continued)
Octal Code
3^
35
36
37
uo
Ui
U2
^3
uu
^5
k6
^7
u
u
o
Mnemonic
STU
SAM
SAL
SEX
cd
LAL
DAV
SRM
H
cd
LRS
SRS
H
M
bO
CD
H
H
<u
H
H
w
CD
FlgMEM
1
1
1
1
1
1
1
1
1
1
1
1
3
p
^ CO
3 u
gEA "
1
y
1
y
1
1
1
1
1
y
1
y
1
y
1
y
1
y
1
1
1
y
1
1
o
CD P
p o
sEA
7
y
E
E
y
y
y
y
y
y
cd cd
O H
CD
sD
7
y
y
y
y
y
y
EM
y
EM
CO
DCRFL
INFL
y
y
y
y
?
y
?
2
C
y
y
y
y
y
y
y
y
CQ
CR
CD
P
cd
DL
1
1
1
1
1
1
1
1
1
1
1
P
CO
EXA
y
y
y
y
y
y
y
y
y
y
y
y
P
3
EXF
y
y
y
y
y
y
y
y
y
y
6
CD
H
EXR
y
y
y
y
y
y
e
y
y
y
y
y
>>
J
i
i
1
i
i
i
i
i
g
N
CD
s
TC
CO
P
cd
P
CO
X
1
1
ZA
A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9 2
1
1
1
1
Control
Step Entry
SI
SI
S2
S2
y
LI
Rl
S3
y
Fl
y
Fl
16 5 
The settings of C, sEA, sD, and the use of gEA are made according to the
desired output of the exponent adder when the first control step following Gl is
initiated. The accumulator exponent is in E while the exponent from memory is
placed in EM by FlgMEM EsEA and gEA place the accumulator exponent in EA while
OsEA and gEA clear EA to zero, The output of the exponent adder (EAD) is then de
termined solely "by the setting of sD and C as discussed in section 3.2.3.
INFL is set to "0" if the order being decoded requires an initial oper
and; otherwise, Gl makes no attempt to set it. EXA, EXF, and EXR are set ac
cording to whether the Q0, (f), or (r) sequences follow [GJ . The set pattern
for J has no clear description, (j)is set to "l" for NOT, LOR, LAL,. DAV, SRM,
and all orders which use the (f) sequence. U)yis set to "1" for all store type
instructions which use the Qy sequence as well as for CSE and CAE. TC is set
to ,: 1" for store clear type instructions and also CSE and CAE. X is set to "l"
for all orders whose least significant octal digit is 7. A is set to "l" for all
logical type orders. 6 and 6 are set to control the choice of MsS and MsA set
tings in the Ck) and \Bj sequences. They are also used to control conditional
paths in the (i), @, (m), (p), (s), and (v) sequences.
To gain a better understanding of the decode logic, we consider the
signal flow on GI (D1276).
In the inactive state, the Gl Eccles Jordan shown on D1276 is set to
"0" (i.e., its "l" side has a "0" or negative voltage output). Consequently,
the A has a "1" output which represents an inactive request. Note also that
the ODIR output is "0". The last control step in the previous order must be Kl, .
K2, D5, D8, E3, or M8 as indicated by the inputs to the restoring AND in the cen
ter of the drawing. Each of these final steps request some of the link mechanisms
whose replies are inputs to the Gl A . However, all of these final steps set OV
to "1" or bypass it to cause OVr to go from "l" to "0" . As shown on D1291,
166
these requests are effective only when ODIR = 0. When OVr and the output of the
restoring AND on DI276 both go to "0", the Gl EcclesJordan is set to "1", but
the output of the associated A is held to "l". ODIR now goes to "l", indicating
that "the preceding order is done and all indicators are ready for inspection by
AC." If a JOV order is present in AC, #5gOV is allowed to go to "0" (shown on
D1291) and set OV to "0". OVr goes from "0" to "l" when #5gOV goes back to
"1". If a JOV order is not present in AC, #5gOV remains at "l" and ODIR = 1
causes OVr to go from "0" to "l", even though the request from the final control
step of the previous order is still active (i.e., still "0").
At the same time, the fact that the Gl EcclesJordan is now set to
"1" permits the EcclesJordan associated with the active control step preceding
Gl to be set to "0" . This does not actually occur until all the requested link
mechanism other than OV have responded with "0" replies and
dec = [(DCRFL)d][(lNFL)d ^ dcrs] = 1. The latter signal is "1" when DCRFL is set
to "1" and either INFL or DCRS is set to "1", indicating that the next order is
in DCR and its operand  if needed  is in Fl (IN).
When the EcclesJordan in the control step preceding Gl is set to "0",
the output of its associated A goes from "0" to "1". This causes the replies
to go from "0" to "1", indicating that the activated link mechanisms are either
off (in the case of gates) or latched in the state requested. When the OVr also
goes to "1" as described above, the output of the Gl A goes from "l" to "0",
initiating the active phase of decode. The requests made by this output depend
on the order in DCR as summarized in Table II.
The "0" output of the Gl A causes the contents of Fl (IN) to be gated
into M and EM, regardless of whether the order being decoded will use this operand.
It also clears Q, and Q, , to "0", and sets CR and ZA t,o "0" (i.e., requests CR
and ZA). It also allows the outputs of the DCR register to be decoded as shown
y
on GII (D1278). Before the output of the Gl A goes to "0", all points in both
167
the instruction decoder (D1278) and status memory decoder (encloder) are held to
"1". The logic of these decoders does not react to the new outputs of DCR until
Glb goes to "0". The GII ( D1278) logic selects the entry control step of the
sequence which follows decode while the GIII (D1277) logic sets the status
memory elements to their appropriate state.
The negative logic for GII is given below. The numbers in brackets
indicate the range of octal digit pairs for which the associated signal is "0".
The f . and f . signals represent the true and complement outputs of the i —
Felement in the DCR.
First Level
G10 s (61  b) v f v f s [0017]
GX  a = GX  b = G12 = (61  b) v f v f v f = [2027]
J &
GY = G13 = (Gl tjv^vfgvf a [3037]
GZ
G17 = (Gl ■ b) v f v f v f a [kOkl]
Second Level
Gl  Bl = GB  a = GB  b = G10 v f = [0007]
GW = Gil = G10 v f = [1017]
Gl  PI = GP = G21 = G13 v f ^ = [3033]
GlU = G13 v f^ = [3U37]
Gl6 = G17 v f ^ v f v f 6 = [1+2]
G18 = G17 v fg = [kl, 1*3, 1*5, 1*7]
I68
Third Level
Gl  Al = GA = Gil v f r  [10, 12, Ik, 16]
Gl  El = GE = Gil v f ' = [11, 13, 15, 17]
Gl  S2 = G2S = GlU s/ f = [36, 37]
Gl  SI = G15 = GlU v f = [3^ 35]
Gl  Rl = (G12)(Gl6) = [2027, h2]
Gl  LI = G19 = Gl8 v f . v f = [Ul]
Gl  S3  G20 = Gl8 v/ f ^ v f = [U3]
Gl  Fl = GF = Gl8 v f , = [U5U7]
The negative logic for GIII is given below. The numbers in brackets have the
same meaning as above. An "x" indicates that any octal digit applies. Note
that some of the variables in this logic are generated above, e. g., GY.
First Level
G30 = G31 = G32  G33 = (Gl  f ) v f k = [x0x3]
G3^ = (Gl a)vf vf ga [x3, x7]
G35 = (Gl f) vf/= [x0, x2, xh, x6]
G36 = (Gl  a) v/ f k  f 6 = [x5, x7]
G3T = (Gl  f ) v f s/ f 6 = [xO, xk]
G38 = (Gl  f ) s, f k v f = [x2, x3]
G39 = (Gl  a) ~ f^ v ? 5 ~ f 6 = [x6]
GUO = Chi = (Gl  a) v fY = [x4x7]
169
Second Level
Third Level
Gl  C = Gi+2 = GE v f = [11, 15]
GU3 = GE v f = [13, 17]
Gl  X = Gl+U = GS^ ^ f ^ = [xT]
GU5 = (GB  a) v/ G36 = [05, 07]
G^6 = G¥v Gl+1 = [1^17]
GU7  (GX  a) v G36 = [25, 27]
GU8 = (GX  b) v GW  [1027]
GU9 = Gi+O vf a [xU, x5 ]
G  50 = GY v f h = [3^37]
G  51 = G36 v G39  [x5, x6, x7]
G  52 = (GB  b) v GZ  [0007, UO^7]
Gl  DL = G53 = GUU v/ GZ = [kJ]
G$k = (GBb) v G35 ^ GiU = [OU, 06]
G55 = (GB  a) ^ G31 = [0003]
G56 = (GX  b) v G^l = [2U27]
G57 = (GY)(G52) = [0007, 3037, ^0^7]
G58 = (GX  a) v G39 = [26]
G59 = G33 ^ Gi+8 = [1013, 2023]
G60 = (GX  b) v G37 = [20, 2U]
170
G6l = G39 v G^9 = [xU, x5, x6]
G62 = G31 v f « [xO, xl]
G63 = G31 vf g = [xl, x3]
G6U = G50 v G51 = [3537]
G65 = G51 v G52 = [05, 07, U5V7]
G66 = GF v GP v G2S = [3033, 36, 37, ^5, ^7]
G67 = GE v GliO = [15, 17]
G68 = GE v/ G33 = [11, 13]
Fourth Level
Gl  C = (GA)(G^3)(G66) = [10, 12lU, 16, 17, 3033, 36, 37, ^5, ^7]
Gl  DL = (GBb)(GY)(G32)(GU8)(G6l) = [001+6]
Gl  J  (GP)(GZ)(G5 1 +) = [ok, 06, 3033, kokj]
Gl  J = (GX  a)(GW)(G^5)(G50)(G55) = [0003, 05, 07, 1027, 3^37]
Gl  N = (G^6)(G56) = [1^17, 2U27]
Gl  N = (G57)(G59) = [0013, 2023, 30U7]
Gl  TC = (G^6)(G58) = [lU17, 26]
Gl  TC = (GU7)(G57)(G59)(G6o) = [OO13, 2025, 27^7]
Gl  X = (G32)(G6l) = [xOx6]
Gl  9 1 = (G38)(G5l) = [x2, x3, x5x7]
Gl  ? 1 = (G37)(G62) = [xO, xl, xk]
Gl  6 2 = (G3^)(G63) = [xl, x3, x7]
■171
Gl  9 = (G35)(G6l) = [xO, x2, xUx6]
Gl  A = (G6U)(G65) = [0507, 3537, ^5^7]
Gl  A = (G32)(G37)(GU8) = [oooU, 103U, U0M1]
Gl  gEA = (GW)(G66) = [1017, 3033, 36, 37, h5, kj]
Gl  OsEA = (GF)(G67) = [15, 17, h5, hi]
Gl  EsEA = (GA)(GP)(G2S)(G68) = [10lU, l6, 3033, 3^, 37]
Gl  OsD = (GP)(G2S) = [3033, 36, 371
Gl  EMsD = (GF)(G^3) = [13, 17, U5, hi]
Gl  EMsD  (GA)(GU2) = [1012, lUl6]
For example, if a clear add type order is in DCR, then the Gl  Bl
output of the GII logic goes from "l" to "0", causing the Bl EcclesJordan shown
on D1270 to set to "l" but holds the output of the Gl A to "l" . The resulting
"0" output on the "0" side of the Gl EcclesJordan is 0R s d with Gl  Bl to yield
a "0" which is returned to the AND in Gl shown at the bottom left corner of GI
(D1276). The output of this AND is OR'd with the output of the larger OR which
collects the replies from the status memory elements that are set by the outputs
of the GIII logic as well as FlgMEMr, (DCRFL)d, and (iNFL)d. A discussion of
the logic associated with the latter two signals is postponed for the present.
Note that gEA, sEA, sD, and C are not requested for {Bj type orders, so their
replies remain at "l". It is clear that when all of the activated replies are
"0", the top input to the AjA will go to "0", causing the AND output to set the
x
Gl EcclesJordan back to "0". This in turn changes the output of the Gl A
from "0" to "1" which initiates the relaxation phase of the decode control step.
If DCR contained an illegal order (kO, kh, or h6) , the GII logic would
not set the entry EcclesJordan of any control sequence. As a result, both
172
inputs to the AA shown on GI (D1276) would remain at "1" so that the AND out
put would remain at "0". This "0" OR'd with the "0" request from the Gl A
would cause the "decode error" indicator to light.
So far, nothing has been said about the output of the "latch" AND
that appears at the right edge of GI (D1276). Its outputs, G2  a, b, d,
and k, go to "0" after the Gl A output goes to "0" during the active phase of
decode.
G2  a, G2  b, and G2  d "unlatch" the OR's shown at the bottom of
GI. The second inputs to these OR's are the replies from those link mechanisms
which are requested by other control steps in DC. The outputs of these OR's are
denoted by primes and feed only the logic shown on GI. Since FlgMEM, N, A, and
9 are requested only during decode, their replies feed the logic on GI direct
ly. The significance of this will soon be apparent.
The "0" G2  d output is also distributed to the entry A of all con
trol sequence which may follow Gl. For example, G2  f is an input to the Bl
A shown on D1270. G2  f = holds the output of the A at "1" even after the
Gl  Bl request goes back to "1" .
The "0" G2  k output sets DCRFL to "0" which returns the "dec" sig
nal to "0" and causes ( DCRFL )d = 0. If dcrs = 0, it also sets INFL to "0"
which in turn causes (iWFL)d to change from "1" to "0". If dcrs = 1, (iNFL)d
is already "0". The ( DCRFL )d signal remains at "1" during this time and con
tinues to inhibit AC from reloading DCR and setting DCRFL back to "1". The
same is true of (iNFL)d if INFL is set to "0" by G2  k.
£
After the Gl Eccles Jordan is set to "0" and the A output changes
from "0" to "1", all nodes and outputs of the GII and GIII logic must return
to "1". In fact, R. R. Shively designed this logic such that its outputs are
"1" only after internal nodes have returned to "1". This logic is said to be
•173
"flushed" to "l" when the replies from the control step entries, gEA, sEA, sD,
C, and all other status memory elements have returned to "1", For any given
order, only one control step entry reply (e.g.., Bl  Gl) goes to "0" so only
one must go back to "l". To check this RP  1 and RP  2 on GI feed the
"latch"' AND, RP  3 and RP  k also feed the "latch" AND to insure that a "0"
is not trapped between the series OR's which gather replies. The need for such
a check when reply OR's are used in series was pointed out by R, E, Swartwout.
When all replies have returned to "l", the output of the "latch" AND
changes from ;, 0" to "1". The latching effect is now clear, The primed reply
signals on GI cannot change from "l" to "0" even though the unprimed replies
will change in response to requests from control steps which follow Gl. The
fact that FlgMEM, N, A; and 9 are only requested by Gl means that the "latch"
AND output remains at 1 until the Gl A output goes to "0" during the next
decode step.
When G2  k goes to "1", (DCRFL)d and possibly (iNFL)d go from "l" to
"0". This allows AC to load DCR with a new order and set DCRFL back to "1" .
The same applies to Fl (IN) and INFL when necessary.
When G2  d goes to "l", the corresponding cable inputs to the entry
A s also go to "l" , For example, in the (BJ sequence (D1270), the G2  f sig
nal goes to "l" If the Bl EcclesJordan was set to "l" by Gl  Bl during the
active phase of decode, the output of the Bl A changes from "1" to "0", initiat
ing the first step (Bl) of the (B) sequence. The decode entry to other se
quences follows a similar pattern
5.2 The Clear Add Sequence vB)
Besides the decode entry to Bl, there are also entries from Al and
S10 as shown on D1270. The entry from Al corresponds to the case where the ad
dend (subtrahend) is so much larger than the augend (minuend) in AQ, that a
17U
CAD (CSB) yields the sum (difference). The entry from S10 has CAD initial con
ditions and represents the second half of an XCH order.
Let m and em denote the contents of M and EM as usual. Remember that
m = m amd enu = env following Gl since the sign bits of the fraction and
exponent are duplicated as they are placed in M and EM via FlgMEM. A is set
to "0" for CSB, CST, CAD, CAT, and NOT. These orders place m, 2m, m, 2m,
and m in A and transfer em to E. Since m represents the bitwise complement of
kk — 10+
m, m = m + 2 and 2m = 2m + 2 . For AND, LOR, and BLS, A is set to
"l". These orders form a • m, a ^ m, and 2a with the sign bit duplicated. The
result is placed in A while the contents of E remain unchanged.
The Qi) sequence sets Z to "0" (i.e., sets Z) and sets KgA = 1 in all
cases. The output of the Aadder, a, represents the assimilated value of the
accumulator, a, at the time of exit to Kl. Because of the CSB, CST, and CAT
orders, cc may be overflowed modulo 2 (a < 1 or a > l) when control is trans
ferred from B3 to Kl. This condition is detected and corrected by the (k) se
quence as discussed in section 5.3.
To acquaint the reader with the logic of DC, we follow the signal flow
through the (b) sequence as shown on D1270.
Assume that the output of the Bl A has just changed from "l" to "0"
following an entry from Gl, Al, or S10. This "0" request from Bl sets the sSR
selector mechanism to OAsSR and causes gS = gR = 1 in the MAU. KgA = 1 at the
time of entry to Gl, so it is still true at Bl. The same is true for the entry
from Al (D1268). The MsA selector mechanism is set to KgA in SI (DI283) and
never reset during (sf), so KgA = 1 when Bl is entered from S10. Consequently,
GC represents the assimilated value of A which is transferred to R when gR = 1.
At the same time, zero is placed in S when gS = 1. Z is set to "0" since the
quantity which is eventually placed in AQ, is generally not zero.
175
If a NOT order is being executed, j = \ = so that an MsS, CS re
quest is sent to the MsS selector mechanism. This causes m to he added to the
th
contents of S without a complement carry in the kk — position. If any other
Bj type order is being executed, j • X. = so that the 0MsS decoder shown on
D1506 is enabled. The settings of 6 and 6 determine the state requested.
Note that AND and LOR request MsS while BLS requests 2MsS. Since S con
tains zero in all cases, the state of the MsS mechanism and the contents of M
determine cr which is the output of the Sadder.
In the EAU, the "0" Bl request sets the sEA mechanism to the OsEA state
and opens gEA, thereby causing EA to be cleared to 0. C is set to "0" and the
sD mechanism is set to the EMsD state,, This causes the contents of EM to appear
as the output, d, of the exponent adder.
While all of this is taking place, Bl  E2 is "0" and thus sets the
B2 EcclesJordan to "l", but at the same time prevents the output of the asso
y
ciated A from going to "0". When the false side (i.e., "0" side) of the B2
EcclesJordan goes to "0", it is set. This is checked by OR'ing it with the
"0"going replies from the activated link mechanisms. When all are "0", the
Bl EcclesJordan is returned to "0" . This is checked by the presence of a "0"
on the true output of the Bl EcclesJordan. This "0" causes the link mechanism
replies to change from "0" to "l" which completes the relaxation phase of Bl
and initiates the active phase of B2,
All entries to [BJ for which X = bypass B2 and make the requests
associated with B3, but do not set "the B3 EcclesJordan. This is accomplished
— x
via a restoring AND following the B3 A . The requests made by this AND are con
sidered later.
A is set to "1" for the AND, LOR, and BLS orders, so the B2 step
is done. The B2  RgM request goes from "1" to "0", thus enabling the conditional
■176
logic shown on RgM (D1191). For the AND order, J v \ = and j v ' ? v \ = 0,
so R • MgM is done while R ^ MgM is bypassed to obtain a "0" reply. Since the
assimilated contents of A were placed in R during Bl, R • MgM produces a bitwise
AND of the assimilated contents of A with the contents of M. The result replaces
the contents M as discussed in section 3.1.2.2. For the LOR order, '
\ ^ 3 '9=0 and j v \ = so that R v MgM is done and R • MgM is bypassed.
This places the bitwise OR of the assimilated contents of A and M in M. For
the BLS order, j v \ = and \ ^ j = so RgM is done as discussed in
section 3.1.2.2. Consequently, the assimilated contents of A  now held in
R  are transferred to M. For all three orders, a must change to match the
new contents of M.
Meanwhile, B2B3 sets the B3 Eccles Jordan to "l" but prevents the
— *
output of the corresponding A from going to "0" . When the R v MgM and R • MgM
replies go to "0", the nonrestoring AND output follows and sets the B2 Eccles
Jordan to "0". This in turn causes the output of the B2 A to go from "0" to
"1", thereby initiating the relaxation phase of B2. When the R • MgM and
R ^ MgM replies change from "0" to "l", the B3 A output goes from "1" to "0",
initiating the active phase of B3.
— *
Note that the output of the B3 A feeds a restoring AND which was men
tioned above in regard to bypassing B2. When the output of this AND changes from
"1" to "0", either the EcclesJordan in B3 is set to "0" and the one in B2 is
still set to "l", or the EcclesJordan in B3 is set to "l" and the one in B2 is
set to "0". In either case, the "0" request from the AND in B3 sets the sAQ
mechanism to SOsAQ and opens gA so that a, which equals the contents of M modi
fied by the state of the MsS selector mechanism, is transferred straight into
A. The MsA mechanism is set to KgA. After the carry generator and Aadder have
responded, Ot represents the assimilated value of as placed in A. At this
177
point, the stored carries in A are all "0" except for a possible carry in A,
when CSB and CST are executed.
For the socalled arithmetic orders (CSB, CST, CAD, CAT, and NOT)
X = so the B3 request opens gQ and DgE. This clears Q to zero and places the
exponent of the incoming operand in E (i.e., the quantity that was placed in EM
during Gl is now transferred to E). For the logical orders (AND, LOR, and BLS),
\ = 1 so gQ and DgE are bypassed. This means that the contents of Q and E remain
as they were during Gl.
Except for BLS, B'j, also requests entry to Kl. The B3K1 signal
is "0" when B3 is active and \Q  0. This signal sets the Kl EcclesJordan to
"1" and causes Kl  f to go to "0" as soon as all the link mechanisms requested
by B3 respond with "0" replies. The Kl logic is shown on D1279. If BLS is the
order being executed, \ v Q = so the B3K1 signal remains at "l" and the Bk
EcclesJordan is set to "1" by the "0" B3B^ signal. The BUB3 signal goes to
"0" as soon as all the link mechanisms requested by B3 respond with "0" replies.
As soon as Kl  f or BUB3 go to "0", the EcclesJordans in B2 and
B3 are set to "0" . One of these is already set to "0" depending on whether or
not the B3 EcclesJordan was set to "1" by a request from B2. In either case,
the result is the same. The output of the AND in B3 changes from "0" to "l".
When the link mechanisms respond with "1" replies, either Kl or Bh becomes active.
Assume for the present that BLS is being executed so B^+ becomes ac
tive. Since the assimilated contents of A during Gl are now shifted left by one
bit position, it is possible for a £ a n . There are no stored carries in A
so a = a, and a = a . If a / a, the Kl step will shift the contents of
AQ one base k position to the right and yield a binary right shift of the orig
— £
inal contents of A. To prevent this, the "0" request from the Bk A opens a gA
i. causes a„gA = in this case) which copies a„ into A . As a result,
a = QL at the time of entry to Kl from Bk. Meanwhile, the BUK1 signal sets
178
the Kl Eccles Jordan (shown on D1279) to "l". There is no reply associated
with a Q gA_ 1 so the "0" output of the Kl Eccles Jordan is sufficient to cause
Kl  d to change from "l" to "0". This signal sets the Bk EcclesJordan "back
to "0", which causes Bk  a Q gA and BUK1 to return to "1". This initiates
the active phase of Kl as described in the next section.
5.3 The Correct Overflow and Detect Zero Sequence \K)
Except for SBE, ADE, CSE, CAE, and premature exits from MPY, DIV,
NDV, and VTD orders, all orders pass through one or more control steps of the
(k) sequence. In all cases, KgA = 1 at the time of entry to Kl, so O. represents
the assimilated value of A. Kl determines whether AQ is overflowed modulo 2
or zero. These conditions cannot both be true. If examination of the most sig
nificant bits of Oi and the state of Z shows that neither of these conditions are
true, Kl sends a bypass request to the OV status memory element and exits to Gl
via KlGl. If QL is overflowed, Kl and K2 right shift AQ one base k position and
check for exponent overflow before exiting to Gl or K3. If a is not overflowed,
Z is set to "0", and the most significant bits of a are zero, Kl and K2 right
shift AQ into SR and check for zero but do not return this assimilated repre
sentation to AQ. In K2, OV is bypassed and Z is set to "1" or bypassed, depend
ing on whether SR is zero or not. Control then passes to Gl or K3 depending
on whether TC is set to "0" or "1".
When SSC or ASC are executed, the (k) sequence is used twice as shown
in Table I. On the first pass through (k) following (A), TC is set to "1" so
K3 may be entered from either Kl or K2. K3 acts as an abbreviated decode step
in that it sets CR to "0", clears Q, and Q. , to "0", and opens the gate to
EXR in the process of activating Rl (D1282).
As a final example of signal flow through control logic, we consider
the (k) sequence in detail.
179
The EcclesJordan in Kl may be set to "1" by an entry request from
any one of eleven different control steps as shown on D1279* Assume the replies
associated with the entry request have gone to "0" and are now returning to
y
"1" . As soon as all reply inputs to the Kl A are "l", its output changes from
"l" to "0", initiating the active phase of the Kl control step.
If (ctov) x z(oaiz) = 0, the contents of AQ, are neither overflowed mod
ulo 2 nor zero. The significance of Oov and Ctoz is discussed in section 3.1.9.
Their values are valid at this point, since KgA = 1, If tc  0, the KlGl signal
requests entry to Gl and bypasses 0V to obtain a "0" OVr as discussed in section
5.1. If the conditions for starting a new decode step are satisfied (i.e., if
dec = l), GlKl changes from "1" to "0" which sets the Kl EcclesJordan back to
"0", beginning the relaxation phase of the Kl step. If, on the other hand,
tc = 1, an entry request is sent to K3. The K2K3 signal goes from "l" to
''0" and sets the K3 Eccles Jordan to "l" which in turn causes K2K1 to set the
Kl Eccles Jordan back to "0". Therefore, when the output of the Kl A changes
from "0" to "l" in the relaxation mode, the Gl or K3 control step becomes active
depending on the setting of TC.
If (cfov)(z v (anz)) = 0, the contents of AQ are either overflowed or
Z is set to "0 ,! and a may b< zero. If Cfov = a © a = 1, a  and hence AQ, 
is overflowed modulo 2, If Cftiz = a v a, v a ^ a ^ a. = 0, a may be zero.
Since z = 0, it is necessary to check every bit of C£ and Q to determine if all
are zero. This is done by examining the outputs of the S and R zero detectors
following a right shift into SR.
When the output of the AND0R defined by Kl v (aov)(z) ^ (aov)(anz)
is "0", it sets the sSR mechanism to the l/k AQsSR state and opens gS. It
also opens gR if DL is set to "l", indicating a double length operation. If
DL is set to "0", gR is bypassed to obtain gRr =0. In the latter case, a
■180
and cci i are lost. DL is always set to "l" except when Kl is entered from D20,
in which case dl = to prevent losing the remainder which is stored in R.
In case 3 addition, CR is set to "1" during a particular pass through
A10 in the (a) sequence, but it is not set to "0" prior to exit from (aV Thus
CR is always set to "0" during Kl to insure that the true sign bit of the un
assimilated number in AQ is copied into S , and S when \ = as discussed in
section 3.1.2.8. If \ = 1, setting CR to "0" insures that "0" is inserted in
S , S , and S when gS = 1. This is in keeping with the fact that oc is con
sidered the leftmost bit at the output of the Aadder when "logical" orders are
executed. In Kl, d is transferred to S when gS = 1. Since KgA = 1, all of
the a bits are "0".
The "0" request from Kl also sets the MsS mechanism to the OMsS state.
This causes the new contents of S to appear as a at the output of the Sadder.
Additional activity occurs in the EAU during Kl. The "0" request sets
EsEA and opens gEA. The exponent, e, associated with AQ is thus transferred
from E to EA. Since this request also sets OsD, the output of the exponent adder
is therefore determined by the contents of EA and the setting of C. If
Qiov = 1, C is set to "l", thereby adding a unit to the exponent in EA. This com
pensates arithmetically for the right shift of AQ, to correct the fractional
overflow condition. The output, d, of the exponent adder (DI503) is e + 1
which may exceed 127. If so, dov = 1 at the output of the exponent decoder
(DI50U) as discussed in section 3.2.4. Otherwise dov = 0. If Ctov = 0, C
is set to "0" since AQ is left as it is, except for a transfer into SR to
check for zero. In this case, d = ea but is not used since the nonoverflowed
branch of K2 does not open DgE.
While the above requests are made, KlK2a. sets the K2 Eccles Jordan
to "l" but prevents the output of the associated A from going to "0" . When
I8I
the replies from the activated link mechanism change from "1" to "0", K2K1
goes from "1" to "0" and sets the Kl Eccles Jordan to "0". At the completion
of the relaxation phase, all replies return to "l", including the KlK2a re
quest. The output of the K2 A then goes from "l" to "0".
The K2 step has a conditional branch in its control path. If c = 1,
Oov was true in Kl, so SR is transferred straight into AQ, d is gated into
E, and 0V is set to "l" if dov = 1. If c = 0, Qtov was not true in Kl, so
SR is checked for zero and 0V is "bypassed to cause OVr = when entering Gl.
First consider the case where c = 1. On D1279 c = 0, so K2 requests
gA and sets SRsAQ which transfers the contents of S straight into A since
OMsS is true. If dl = 1, gQ is also opened so that R is transferred straight
into Q. In the case of divide orders dl  0, so gQ is bypassed leaving Q un
changed and in fact zero. This K2 request also opens DgE and thus transfers
the new accumulator exponent, e + 1, into E. If z = and dov = 1 as dis
cussed above, 0V is set to "l". However, if z = 1 but dov = 1, 0V is not
set to "1" but is bypassed. This is to prevent setting 0V to "l" when Z is
already set to "l". (This rule is violated when the accumulator contains
zero and a VID order is executed. The exit to Gl via D5 sets 0V to "l".)
If dov = 0, 0V is always bypassed. At the same time, the EcclesJordan in
Gl or K3 is set to "l" depending on whether TC is set to "0" or "l".
When gAr ^ gQr ^ DgEr v sAQr v OVr v (GlK2a) [ (K2) v (tc) ^ K3K2] = 0,
the K2 Eccles Jordan is set to "0". After all the requests and replies have
returned to "1", the active phase of Gl or K3 is initiated.
Now consider the case where K2 is active and c = 0. If the outputs
of both the S and R zero detectors are "1", SZ v RZ = 0, so Z is set to "1".
Otherwise, Z is bypassed. The S and R zero detectors appear on ZDR (DI505).
0V is always bypassed in this case. The EcclesJordan in Gl or K3 is set to
"1" depending on whether TC is set to "0" or "1".
I82
When Zr v (GlK2b) [(K2) v (tc) v (K3K2)] = 0, the K2 Eccles Jordan
is set to "0" . As before, when all K2 requests and their corresponding re
plies return to "1", the active phase of either Gl or K3 is initiated.
Since the Gl control step is described in section 5.1* we consider
K3. This control step is active only during the first pass through (k) in
the execution of an SSC or ASC order. Its primary purpose is to open the OR
gate to EXR and set the Rl Eccles Jordan to "l" as shown on D1282. EXR is
set to "1" if (z v dl)(na)(za ^ dl)(n * 9 ^ 9 v QZ)(J ^ QZ) = 0. Since K3
may be activated from Kl, CR may still be set to "1". As discussed in section
3.1.12, it is necessary to set CR to "0" to insure that Oi and a represent
3
the true sign bit of A in the event of a right shift into S with KgA = 1.
It so happens that this condition never arises in passing through \RJ and
\SJ in completing and SSC or ASC order. It may happen during the second pass
through [KJ on the way to Gl, but if so, CR is set to "0" during Kl or Gl.
As an afterthought, therefore, the request to set CR to "0" in K3 is not
necessary. The 0gQ,« _Q. . request is necessary to make SSC and ASC consistent
with the order pairs SUB, STC and ADD, STC.
When the Rl EcclesJordan is set to "1", EXRr = 0, and CRr = 0,
R1K3 changes from "1" to "0" and sets the K3 EcclesJordan back to "0".
When the K3 requests and replies return to "1", the Rl control step is ac
tivated. Its requests are discussed in section 5.10.
5.k The Load Q Sequence (l)
This sequence is used only by the LAL order. Its function is to
load Q (i.e., the least significant half of the accumulator) with a fraction
al operand but leave A unchanged. The accumulator exponent in E is also left
unchanged. Since Z is set to "0" even though A may contain zero, control
I83
passes through (k) on the way to Gl. If A is zero and a zero fraction was
placed in Q by (l\ then K2 detects this and sets Z to "1". Thus, when Gl
is activated to decode the next instruction, Z is set to "1" if AQ contains
zero in any form. If the exponent in E is less than 128 at the beginning of
an LAL order and the operand placed in Q is nonzero, then K2 will not set Z
to "1" even though the entire accumulator is considered zero under other cir
cumstances.
The description of the (l) sequence and each of the remaining se
quences is abbreviated. The effect of each control step on the AU and LM is
discussed, but a description of the signal flow through the sequence logic
is omitted.
The Gl entry to LI is shown on D1280. Since KgA = 1 is an ini
tial condition for Gl and since the state of the MsA mechanism is not changed
during Gl, a represents the assimilated contents of A at the time LI becomes
active.
During LI, CC is placed in R and S is cleared to zero. MsS is re
quested so that the fractional operand in M appears as (i.e., output of the
Sadder) by the time L2 becomes active, Z is set to "0" to cover the case
where Z is currently set to "1" but the operand in M is nonzero.
As mentioned above, this does not cover the case where Z is true
because of exponent underflow at the time of entry to LI.
During L2, ha is placed in A. This means the sign bits of the
fractional operand in M are lost. Furthermore, r and r are placed in
Ai _ and A, , . These bits, incidentally, are equal to the sign bit of oc as
it appeared at the output of the Aadder during LI.
In L3, the contents of R are transferred to M via RgM as dis
cussed in section 3.1.2.2. During this step, the zero stored carry bits
in A flush through the carry generator and Aadder logic. After this
18U
occurs, the new contents of A (i.e., the fraction that is to be placed in Q)
appear as a.
In LU, a is placed in R. Remember that oc > R ... a, , * R, , .
Note also that a, = a., represents the true sign bit of the accumulator as
it appeared during LI and is therefore noise as far as the fractional oper
and from M is concerned. During L3 and iA, the new contents of M  namely
the old assimilated contents of A  appear as o since S contains zero and
MsS is still true.
During L5, SRsAQ is requested as the new state for sAQ and both
gA and gQ are opened. As a result, a is placed in A and the contents of R
are placed in Q. In this transfer a. > A. and r. *■ Q. .
1111
At the completion of L5, the original  possibly unassimilated 
contents of A are returned to A in assimilated form, and the nonsign bits
of the fractional operand that was placed in M during Gl are in Q , Q ... Q> ,
Q, and Q, , hold the same bit as A and A at this point. However, Q, and
Q, , are cleared to zero by OgQ^o^kk c ^ ur i n S the Gl following (KJ. Z is set
to "1" during K2 if AQ contains zero.
5.5 The Add Sequence (A
The (a) sequence performs floating point addition (subtraction).
The number in AQ which may be unassimilated during Gl, and its exponent in
E correspond to the augend (minuend) while the fraction in M and its exponent
in EM correspond to the addend (subtrahend). Before the addition (subtrac
tion) is performed, the augend (minuend) is shifted in AQ so that its expo
nent agrees with the exponent of the addend (subtrahend). In case the addend
(subtrahend) is much smaller than the augend (minuend), the fraction in M
is placed in A and shifted right until the exponents agree.
I85
Let the exponent of the augend (minuend) be denoted by ea. Even
though it is in E at the beginning of Gl, it is transferred to EA during the
decode step. Since the exponent of the addend (subtrahend) is placed in EM
during decode, let it be denoted by em. EMsD is the state of the sD mechanism
and C is set to "0" at the time (X) is entered from either Gl or V4. There
fore, during Al the output of the exponent adder is d=ea  em 1. The five
cases of floating addition (subtraction) are defined in terms of d at this
point. Note that d is always a unit less than the true difference between
the exponents of the augend (minuend) and addend (subtrahend).
Case 1: fa #1 = (d < 46) v dz = 1 (i.e., condition is true)
Case 2: fa #2 = (45 < d < l) = 1
Case 3: fa #3 = (0 < d < 21 ) = 1
Case 4: fa #4 = (22 < d < 43) = 1
Case 5: f a #5 = (44 < d) v dov = 1
It is convenient to decode cases 2 and 3 together.
Case 2, 3: fa #2, 3 = (45 < d < 21 ) = 1
The signals fa #1, fa #2, 3, fa #4, fa #5, dov and dz are outputs
of the exponent decoder as shown on D1504 and discussed in section 3.2.4.
Remember that if dz  1, then d <  128, If dov = 1, then d > 127.
If fa #1 = 1, the actual difference in exponents, d = d + 1, is
: 45. This means the augend (minuend) in AQ must be shifted right at
least 45 base 4 places before addition (subtraction) occurs. Since there
are only 45 nonsign base 4 positions in AQ, the fraction in M is simply clear
added (subtracted) via the (b) sequence. Consequently, if the original ac
cumulator was negative, the sum (difference) is too large by at most 2 ' .
If fa #2, 3=1 and d < 0, the actual exponent difference is in
the range: 44 < d CO. Case 2 requires that the contents of AQ be right
186
shifted from to hk base k positions, before addition (subtraction) occurs.
The sum (difference) has the exponent of the addend (subtrahend), i.e., the
exponent in EM.
If fa #2, 3=1 and d > 0, the actual exponent difference is in
the range: 1 < d < 22. Case 3 therefore requires left shifting the contents
of AQ 1 to 22 base h positions before addition (subtraction) occurs. Since
the sum (difference) has the exponent of the augend (minuend), i.e., the ex
ponent in E, the partial result must be right shifted the same number of base
h positions with the appropriate propagation of carries or borrows. Cir
cular left and right shift paths at the high end of A and S and the low end
of Q and R are used to accomplish this c As discussed in sections 3.1.2.6,
3.1o2.8, and 3.1.12, these paths are opened by setting CL and CR to "l".
If d = 22, the contents of AQ, are circularly left shifted until
the two least significant nonzero bits that were originally in Q, and Q,
are placed in A, and A« . . The a and a bits that appeared at the output
of the Aadder during Gl with KgA = 1 are in Q. and Q at the time of addi
tion (subtraction). As the result is circularly right shifted, the Q and R
halfsubtractors (section 3.1.12) propagate a borrow to the left if neces
sary. The rate at which a carry is propagated to the left is exactly equal
to the rate at which the result is shifted right. Thus , as long as a car
ry is being propagated to the more significant bits of the result, A and
S both contain a "1".
If fa jfh = 1, the actual exponent difference is in the range:
23 < d < kh. Consequently, the contents of AQ, would have to be left shift
ed from 23 to hk base k positions. This is generally not possible using the
circular shift techniques described above. Instead, the contents of A and
Q are interchanged, and A is isolated. The new contents of A and the con
tents of M are then interchanged with M being placed in A if a subtract
I87
order is being executed. This is done by steps A2 through A7 in (1\) . The
addend (subtrahend) that is now in A is right shifted d  23 = d  22 base
k positions  leaving Q unchanged  before addition (subtraction) occurs.
The result represents the least significant half of the sum (difference)
with a possible carry or borrow to be propagated into the most significant
half of the addend (minuend) which is presently in Q. After A and Q, are
transferred to R and S respectively, the carryborrow logic described in
kk kk
section 3.1.13 determines whether +2 or 2 should be added to the
contents of S (i.e., the most significant half of the addend (minuend)).
The final sum (difference) is gated straight into AQ and assigned the ex
ponent of the augend (minuend). This final interchange and carry borrow
correction occurs in steps All through AlU of the (l£) sequence as shown on
D1269.
t
If fa #5 = 1, "the actual exponent difference is: d > k^ . This
means the quantity in M should be added (subtracted) to those bits of AQ
1
lying to the right of Q, . If d = U5, the bits in M and M should be
added (subtracted) to the bits in Q, and Qi^. Since these bits are always
set to "0" during Gl, the Cm sequence is simply bypassed in this case and
the augend (minuend) with its exponent is accepted as the sum (difference)
even though Z may be set to "1".
The descriptions given above apply to SUB, ADD, SSC, and ASC.
It should be clear that if the addend (subtrahend) in M is zero (i.e.,
em = 6k) the (a) sequence is bypassed and the augend (minuend) is always
taken as the sum (difference). In the stepbystep description given be
1
low, note that when d is odd (d even) the addition (subtraction) is to
A while if d is even, it is to S.
In Al, the negative conditional logic shown below is used to de
termine the particular case of addition. This logic and the first eight
188
control steps of A appear on D1268.
FA #1 = (em = 61+) v 7(f a #l) = AlBl
FA #2, 3 = (em = 6k) v z v (fa #2,3) => A1A8
FA #U = (em = 6k) ^ z s ' (fa #U)
FA #5 = (em = 6U)[z v f a #5 ] = A3K1
If FA #1 = o, the EcclesJordan in Bl is set to "1" since a CSB
or CAD is required either because Z is set to "1" or fa #1 = 1. After the
Al EcclesJordan is set to "0" by BlAl, the Bl control step becomes ac
tive, Note that nothing is done to the LM or AU during this option of the
Al step. It is designated as a "null" step on the DC Flow Chart. This step
is necessary because Bl clears EA to zero, which may cause the fa #1 out
put of the decoder to change from "1" to "0" and thus destroy the entry re
quest. In other words, if the Bl requests were made in series with entry
request, FA #1 = 0, without setting the Bl EcclesJordan, FA #1 might change
from "0" to "1" before the Bl step is completed and thus cause an error. By
setting the Bl EcclesJordan to "1" first, FA #1 may change from "0" to
"1" during the active phase of Bl and not affect the result. The operation
of the (b) sequence is discussed in section 5.2.
If FA #2,3 = 0, neither the accumulator nor the operand are zero,
but fa #2,3 = 1. The A8 EcclesJordan is not affected, but the A9 Eccles
Jordan is set to "1" and the MsA mechanism is set according to the output of
the 6 decoder (see section 3.1.1^0 if d = 1. In this case, addition (sub
traction) occurs immediately because the exponents of the accumulator and
operand agree. The A9m signal sets the Al EcclesJordan back to "0" in
this case. The activity in the add loop (A9 and A10) is described after
the last two options of Al are considered.
.189
If FA fik = 0, neither the accumulator nor the operand are zero,
but fa #U = 1. As indicated above, a preliminary shuffle of the contents
of A, Q, and M is necessary in this case. The details of this shuffle are
given below.
In A2  which is a particular extension of the Al request  the
assimilated contents of A (KgA = l) are placed in R while the contents of
Q are placed in S. OMsS is set so the new contents of S appear as a. In
the EAU, d = ea  era  1 is placed in ES. The Ak EcclesJordan is set to
"1". When all replies are "0", the Al EcclesJordan is set to "0", causing
the A2 request to go to "1".
When Ai+ becomes active, the contents of S and R are transferred
straight into A and Q. OMsA is set so that the new contents of A appear
as oc. In the EAU, d is transferred from ES to EA and 22 is subtracted from
it by setting 22sD. Consequently, the new output of the exponent adder is
d = d  22 where d = ea  em  1 during Al.
In A5, oc is placed in R and zero is placed in S. The MsS mech
anism is set according to the output of the decoder so that a = m if SUB
or SSC is being executed, while a = m is ADD or ASC is being executed. At
the same time, d is placed in ES.
During A6, + m is placed in A and is set to "1", indicating
that the new contents of M are to be added to the contents of A. DL is set
to "0" to insure that gQ and gR are bypassed during A9 and A10. This iso
lates the most significant half of the augend (minuend) which is held in
Q. In the EAU, zero is placed in EA and d is placed in EM. EMsD is set
with C still set to "0" so that d  1 = ea + em + 22 appears at the out
put of the exponent adder. Since 22 < d.  1 < 1, the quantity in A
(i.e., + m) is right shifted by the add loop (A9, A10) as in a case 2
addition.
190
A comment is in order concerning d  1. Since 23 left shifts
of the augend (minuend) were effectively performed by the interchange of A
and Q, the remaining number of left shifts for Q is given by
< ea  em  23 < 21. Instead, the addend (subtrahend) is right shifted
by the same amount. Because the conditional logic of A9 and A10 is based
on an exponent difference that is one less than the true difference,
(ea  em  23)  1 = ea + em + 22 must appear at the output of the Dadder
at the time A9 is entered.
In A7 the least significant half of the augend (minuend) is placed
in M. Control passes to A8 where the activity was described in connection
with the FA #2,3 option of Al.
If FA #5 = in Al, the request A3K1 bypasses Ck\ and sets the
Kl EcclesJordan to "1". In this case, the operand is zero or the accumu
lator is not zero and fa #5 = 1. A null step between Al and Kl (i.e., A3)
is necessary because the gEA in Kl may remove the entry request. The Kl  b
signal sets the Al EcclesJordan to "0" which then activates the Kl control
step.
We now consider the add loop which contains the A9, A10, and All
control steps as shown on DI269. When the A9 EcclesJordan is set to "1",
the output of the Dadder lies in the range: U5 < d < 21. If U5 < d < 1,
AQ, or A is shifted right d + 1 base h places prior to the addition (sub
traction). Bits' are lost at the right end of Q or A depending on whether
DL is set to "l" or "0". If < d < 21, AQ is circularly left shifted by
d + 1 base h places prior to the addition (subtraction). The result is
then circularly right shifted with carries or borrows propagated to the
left .
Since A9, A10, and All constitute an inner control loop, it is
necessary to consider the signal flow through it. The entry logic is
191
somewhat nonstandard in order to start shifting AQ, as quickly as possible
when FA #2,3 = 0, For example, if d / 1 in A8, the A9 EcclesJordan is
set to "1" immediately. Its "0" output, A9  m is used to set the Al Eccles
Jordan to "0" and thus cause A8A9 to change from "0" to "1". However, the
y
output of the A9 A goes to "0" as soon as the EcclesJordan in A9 is set to
"1" and does not wait for A8A9 to change from "0" to "1". In all other loops
the signal which is analogous to A0A9 also feeds the A so that it must
change back to "1" before the first step in the loop can become active.
There are two cases in which the start of A9 is inhibited in this manner.
If FA #2,3 = and d = 1, the MsAr must to to "0" before the A9 Eccles
y
Jordan is set to "1", so the A9 A cannot go to "0" until the Al Eccles
Jordan has been set to "0" and MsAr returns to "1". A similar statement
applies if the A8 EcclesJordan is set to "1" at the time A8A9 changes
from "1" to "0".
In all control loops the EcclesJordan that is analogous to A9
is set to "1" when the loop is entered. It remains at "l" as long as the
exit condition is not satisfied (i.e., ex = 0). The ex and ex signals feed
— x
the A s analogous to All and A9 respectively. These signals may come from
the EXA, EXF, or EXR status memory elements as discussed in section U.3. As
— *
long as ex = 0, the output of the All A or its equivalent is held to 1
— *
while the A9 and A10 A s or their equivalent alternately become active and
— *
relax. When ex changes to 1 during A10, the output of the A9 A is held
to "1" and the output of the All A goes from "1" to "0" instead. This ul
timately sets the A9 EcclesJordan back to "0".
While control alternates between A9 and A10, the A1C EcclesJordan
— *
is alternately set to "0" or "1". When the A9 A first becomes active, the
A10 EcclesJordan is set to "0". The replies from the link mechanisms
192
requested by A9 go to "0" and set the A10 Eccles Jordan to "1". This cannot
occur unless the A9 Eccles Jordan is set to "1" (i.e., not unless A9  m = 0)
When these replies return to "1", the output of the A10 A goes to "0". The
link mechanisms which it requests send back "0" replies which cause the A10
EcclesJar dan to set to "0". The A10 request and associated replies return
to "1". If exa = 0, A9 becomes active and the process is repeated. If
exa = 1, All becomes active and sets the Eccles Jordan in either Kl or A12.
This combined with "0" replies from CL and possibly MsS set the A9 Eccles
Jordan back to "0". When the add loop is terminated, the A9 and A10 Eccles
Jordans are both set to "0".
The conditional logic associated with A9 and A10 is complicated
by the presence of bypass signals called "bya" and "byb" . These signals
are used to generate bypass requests for selector mechanisms and certain
status memory elements after the shift paths have been established and the
only activity is opening and closing the gates in the MAU to shift and in
the EAU to count. The negative logic for these signals is given below.
bya = (ESsEA) v edc
byb = ft ^ (es = 3) v (es = 2) ^ (es = l) ^ (es = 0)
^ (es = l) v (es = 2)(cr)
The ESsEA signal is generated by the sEA mechanism as shown on DII85.
The Q and cr signals are outputs of the status memory elements of the same
name. The edc signal and the (es =) signals are outputs from the EDC F
element and ED register as shown on EDM (DI50U).
Perhaps the best way to describe the action during A9 and A10
is to consider two examples. In the first example let d = 3 so that AQ
or A is right shifted 2 places before addition (subtraction) occurs. In the
193
second example let d = 2 so that AQ, is circularly left shifted 3 places
before addition (subtraction) occurs and then circularly right shifted the
same number of places .
Assume d = 3 when A9 first becomes active. Note bya = since
the sEA selector is set to EsEA during Gl. Remember KgA was true during
decode and is still true. The sSR mechanism is set to l/U AQsSR and CL is
bypassed. The MsS mechanism is set to OMsS, If case 2 addition applies,
DL is set to 1 so both gS and gR are opened causing the assimilated contents
of AQ to be right shifted into SR with the sign bit, a , duplicated in S
and S . If case k addition applies (case 2 or case k must apply because
d < 0), DL is set to "0" so only the assimilated contents of A (i.e., a) is
right shifted into S with CCi and (X , being lost. In either case, the new
contents of S appear as a at the output of the Sadder because OMsS is set.
In the EAU, gES is opened so that 3 is placed in ES. Note that
gES always gates the ED register as well. Since ESsEA is not true during
the first pass through A9, fl is set to "1". If dl = 1, EMsE is set and gE
opened so the exponent of the addend (subtrahend) is transferred to E as the
exponent of the sum (difference). If dl = 0, case k applies and the expo
nent of the augend (minuend) in E is also the exponent of the sum (differ
ence), so E is left unchanged  gE and sE are bypassed. With this accom
plished, control passes to A10.
During this first pass through A10, byb = because es = 3.
Both gA and gQ are opened if dl = 1, only gA is opened if dl = 0. The sAQ
mechanism is set to l/U SRsAQ and the MsA mechanism is set according to
the 9 decoder output. Addition (subtraction) occurs at this point because
the accumulator has been shifted right 2 places as required. Therefore,
a represents the unassimilated sum (difference). It is necessary to pass
through A9 and A10 again to place this sum (difference) in A.
19^
In the EAU, gEA is opened at the same time as sEA is being set to
ESsEA. Thus, 3 is placed in EA. Note that the sEA mechanism was previously
set to EsEA or OsEA. Therefore, depending on the timing of the gEA signal, the
initial inputs to the EA register may be incorrect. The gEA signal also opens
the EDC Felement gate. In this case the EDC Felement is set to
EDC = (es = U)(es = 0)(es = l)(es = 2) = 1. The ESgEM gate is bypassed because
es = 3. CR is bypassed and 2sD is selected. This causes the output of the ex
ponent adder to become 1 since C was set to "0" during decode.
The sum (difference) is not in AQ or A at this point, so the "done"
signal is "0". In positive logic:
done = (es = 2) v (es = l) ^ Q(es = 0) ^ cr(es = 2)
When "done" is "0", EXA is again set to "0". Notice that EXA is set to "0" dur
ing Gl and Vk as well to prevent immediate exit from the add loop. With exa = 0,
the A9 step again becomes active.
During this second pass through A9, bya = 1 because sEA is set to
ESsEA and edc = 1. Therefore, gE, sE, MsS, sSR, and CL are automatically by
passed with selector mechanisms and memory elements retaining their old state.
Since bypassing yields fast replies, this pass through A9 is termed "fast".
If both the gS and gR gates are opened, the unassimilated a representation and
the contents of Q are shifted right into SR with q, and q, , being lost. If
only gS is opened (i.e., dl = 0), OCs and a, , are lost. This is of no conse
quence since these bits are cleared to "0" during the following decode step.
The gES gate is opened, so 1 is placed in ES. (EMsD)(ESsEA) = 1 in positive
logic, so Q is set to "0". With this accomplished, control passes to A10.
During this second pass through A10, es = 1 so byb = 0. The
■195
sAQ mechanism is set to USRsAQ. If gA and gQ are both opened, the sum (dif
ference) is left shifted into AQ with "0" "being placed in Q, and Q^r. If
dl = 0, only gA is opened and the single length sum (difference) is left
shifted into A with "0" being placed in A, and A, , . The "done" signal is
"1" because es = 1, so the MsA mechanism is set to KgA, and EXA is set to
"1".
In the EAU, gEA places 1 in EA. The sD mechanism is again set
to 2sD, so d = +1 although it is not used. ESgEM is again bypassed. With
exa = 1, All now becomes active instead of A9.
If dl = 1, case 2 addition was performed so CL is set to "0".
This action is unnecessary in this instance but necessary for case 3 addi
tion. Control now passes to Kl. The (k) sequence may find OL overflowed
(i.e., Cfov = l) or AQ, zero.
Assume dl = at All. This implies that case h addition was per
formed, so some terminal operations are necessary . CL is set to "0" only
to obtain a "0" reply, since CL is never set to "1" in A9 when dl = 0. The
MsS mechanism is set to OMsS for use in A12. The carry borrow logic mean
while has examined the Ot , m , and m bits as described in section 3.1.13.
The gCB gate is opened in All to allow the output of this logic to be stored
in the CB Felement .
In A12 the most significant half of the augend (minuend) is placed
in S and the least significant half of the sum (difference) is placed in R.
A carry, a borrow, or nothing is now added to the kh — position of S. The
positive conditional logic which determines whether a carry, a borrow, or
nothing is added appears below.
kk
(cb)(m Q ) =1 > Add 2
(cb)(m ) =1  Add 2
196
cb = 1  Add Nothing
The cb signal is the true output of the CB Felement and m n is the — bit of the
M register. Since the M register contains the least significant half of the
augend (minuend), m and m both have positive weight at this point and are not
hk
necessarily equal. To add 2 ,By MM and CS requests are sent to the MsS mech
anism. (See section U.2.) To add 2 , MMsS, CS is the setting requested. If
nothing is added, By MM and By CS requests are made to cause MMr = CSr = 0, but
the state of the MsS mechanism is left at OMsS as established in All. The most si<
nificant half of the sum (difference) appears as a.
During A13, o and the contents of R are transferred straight in AQ,
and DL is set to "1". Since KgA = 1, the assimilated representation of A ap
pears as OC.
In AlU, the MsS mechanism is cleared to the OMsS state by a KMsS re
quest. This is necessary if MsS was set to MMsS or CS during A12 as discussed
in section J+.2. Control then passes to Kl.
We now return to the second example. Assume d = 2 when A9 becomes ac
tive for the first time. This implies a case 3 addition in which AQ is circu
larly left shifted by three places, M is added (subtracted), and the sum (differ
ence) is circularly right shifted three places. This means the addition (sub
traction) is done with the Sadder. Furthermore, in this particular case
bya = byb  for all steps in the loop.
During the first pass through A9, UAQsSR is set and CL is set to "l".
As discussed in section 3.1.2.12, this opens the paths a. , + R^o and a * R L,V
The gS and gR gates are both opened, so a circular left shift of one base k po
sition occurs. Note that KgA = 1 so a is assimilated, ft is set to "l". The
ES register is set to +2 when gES is opened. The gE and EMsE requests are by
passed because the exponent of the augend (minuend) in E is also the exponent
197
of the sum (difference). The MsS mechanism is set to OMsS. Control passes to
A10 when this is accomplished.
During the first pass through A10, USRsAQ, is set since CR was set to
"0" during decode and es = 2. Because CL is set to "1", the paths a , » Q« _ and
a * Q, , are now open. When gA and gQ are opened, another circular left shift is
performed, placing the result in AQ. The four most significant hits of the as
similated augend (minuend) are in Qi , Sio> ^kv an ^ ^kk a ^ this point. OMsA is
set and EXA is set to "0" because es = 2 and CR is set to "0".
In the EAU, +2 is placed in EA and EM from ES. The latter transfer is
made to save the count for the number of circular right shifts necessary follow
ing the addition (subtraction). The sD selector is set to 2sD while CR is by
passed  meaning that CR retains its "0" setting. As a consequence of 2sD and
C being set to "0" during decode, d = now appears at the output of the expo
nent adder. Control returns to A9 since exa = 0.
During this second A9 step, another circular left shift is performed
with the MsS mechanism being set according to the output of the Q decoder. The
sum (difference) then appears as a in unassimilated form. The gES gate places
d = into ES. Q is set to "0". At the same time, the R halfsubtractor logic
begins to inspect the outputs of R, , R^r, S , and the t input to the high S
special adder. As indicated in section 3.1.12, this information is sufficient
to determine whether a unit must be borrowed from the bit of the augend (minuend)
that is now in R^* If so, a unit is borrowed from R^, R^k during the next A10
step in which a circular right shift of one base h position occurs. If both R,
and R, , contain "0", the borrow is propagated by placing a bit in Am during A10.
During the second A10 step, l/i+SRsAQ is requested and CR is set to "l".
OMsA is requested and EXA is set to "0" because (es =t 0) and ft = 0. Note that
even though cr changes from "0" to "1", l/USRsAQ, is set because es = 0. Since
198
cr = 1, the paths a » A and a * A are now open. Therefore, when gA and
gQ are opened, the sum (difference) is circularly right shifted one base h po
sition into AQ, with borrow propagation. The signals a and a represents the
outputs of the R halfsubtractor as discussed in section 3.1.12. If a borrow is
' • * *
necessary, r> = r, , = 0,a=a=l and Q.i is set to 1 . Otherwise, Qii
is set to "0".
In the EAU, gEA is performed while ESgEM is bypassed. EMsD is requested,
so d = +2 since EA now contains and C was set to "0" in decode. Control returns
to A9 because exa = 0.
During the third pass through A9, the sum (difference) is circularly
right shifted one more base k position into SR with a unit borrowed from Qkoj
Q., if Q,> contains a "1". Since l/^AQsSR is requested and CR is set to "1",
the paths OL > S and OL > S are now open. As discussed in section 3.1.12,
t !
OL_? and OL are two outputs of the Q halfsubtractor. OMsS is requested since
d = 2. Furthermore, ft is reset to "1" because EMsD is the present state of the
sD mechanism. The d = +2 output is placed in ES via gES. The CL memory element
is bypassed but remains set to "l". Control now passes to A10 for the final step
in the loop.
During the third and final pass through A10, the last circular right
shift places the unassimilated sum (difference) in AQ. The "done" signal is now
"1" because cr(es = 2) = 1. Thus, KgA is requested and EXA is set to "l". In
the EAU, +2 is placed in EA, 2sD is requested. The Dadder output is now zero.
Since Q, is set to "l" and es = 2, ESgEM is performed again, but this does not
affect the count. Since exa = 1, control now passes to All.
In All dl = 0, so CL is set to "0" and control passes to Kl. Since
KgA was requested during the last pass through A10, OL is assimilated, so the
Cfov and Cttiz signals are reliable when Kl becomes active.
199
A short summary of the shift patterns in the add loop for 6 < d < 5
is given "below. The letters "F" and S" denote "fast" and "slow" steps depend
ing on whether the bypass signals bya and byb are "1" or "0".
d = ea  em  1
ea = augend (minuend) exponent
em = addend (subtrahend) exponent
For Cases #2 and #k
d =* 6
es
= 6
es
= h
es = 2
d = 5
SR
es = 5
es = 3
es = 1
AQ
d = 5
d = 3
d = 1
d = h
SR
es
= h
AQ
es = 2
d = h
d = 2 d =
•200
SR
es = 3
es = 1
d  3
AQ
d = 3
d = 1
SR
d = 2
AQ
es = 2
d = 2 d =
SR
d = 1
AQ
es = 1
d = 1
es =
d =
SR
AQ
SR
AQ
d =
201
a = 1
SR
AQ
es = 2
a = o
SR
AQ
es = 1
a = 2
(i = i
Sj This shift is
slow because
ESgEM occurs
with EMsD.
a = 2
SR
es =
es = 2
AQ
SR
AQ
a = 2 a = o
•202
(f) This step is not truly fast
since ft is set to "0" .
SR
es
= h
es = 2
AQ
d = 3
SR
AQ 
a = h
a =» i
a = 3
SR 
es = es = 2
= k
AQ
aa
SR
AQ
203
a = 5
SR
AQ
SR
AQ
es
es = 2
d  6
d = 1
a  3
a = 5
This summary shows that for d < 7 and d > 6, at least half of the
steps in the add loop are faster as a consequence of the bypass signals, hya
and byb .
5.6 The Exponent Arithmetic Sequence (jC
This sequence is used only by the SBE, ADE, CSE and CAE orders. It
is entered directly from Gl in all cases as shown on D1270. The exit from E3
always returns control to Gl.
During Gl, the C memory element and the sEA and sD selector mechanisms
are set such that the Dadder output is:
d = ea  em SBE
d = ea + em ADE
d = em CSE
d = em CAE
In this notation, ea represents the accumulator exponent which is also held in
E.
20U
m
The d output as defined above may change when El becomes active. In
Gl, the FlgMEM gate places Fl, in both EMg and EH,. At the same time, Fl. . is
placed in M, « . If eight bit exponents are being used, the bit in M. , is the
true sign bit of the exponent in EM. To effect its transfer to EH,, the
,, , gEH, gate is opened when El becomes active. This may cause d to change.
When E2 becomes active, d is placed in E as the new exponent of the
accumulator. This output is also inspected by the exponent decoder. If d < 128,
a "1" is gated into the ESZ Felement of the ED register. This gating is done
by gED = gES ^ DgE as discussed in section 3.2.U.
When E3 becomes active, Z is set to "1" if esz = 1 and is bypassed other
wise. OV is set to "1" if esov = 1 and Z is set to "0". It is bypassed other
wise. Control then passes to Gl.
5.7 The Store Sequence (S
As shown on DI283 and D128U, the (s) sequence has entries from Gl,
PI, Fk, and R3. The normal entry to (i) is via SI. SAM and STU enter SI dir
ectly from decode. STR, XCH, STC, and STN go through (g) and (r) and then en
ter SI. This is done to normalize the fraction in AQ, (i.e., insure that
1 < f < l/h, f = 0, or l/k < f < l) before A is rounded, assimilated and stored.
Note that XCH involves a terminal clear add operation. The SSC and ASC orders
are equivalent to SUB or CSB, STC and ADD or CAD, STC respectively except Gl does
not become active between the subtraction or addition and the store clear oper
ation. For STF, SIF, SEQ, and SIA control enters the (5) sequence from Gl and
then passes through (f) to SI. In (f) AQ, is shifted right or left until its ex
ponent is equal to the value specified (i.e., until e = for STF, e = 22 for SIF,
e = m during Gl for SEQ, and e = 6 for SIA). If e = during Gl when STF is
decoded, control passes from PI to SI directly. The first nonstandard entry is
205
S2. This entry is used by the SAL and SEX orders. The second nonstandard en
try is S3 which is used only "by the SRM order „
Consider AQ, and E at the time SI becomes active. Regardless of what
preceded the SI step, the assimilated contents of A and the seven least signif
icant bits of E will be stored in FO (OUT) during S9 with or without modifica
tion due to fractional overflow, normalization, or zero corrections. The STU,
STR, XCH, STC, STN, SSC, ASC, STF and SEQ orders round the contents of A prior
to storage in FO. The roundoff logic is discussed in section 3.1»7« It should
be noted that roundoff by itself does not change the SI contents of A. However,
the XCH, STC, STN, SSC, and ASC orders do change the SI contents of AQ and some
times the SI contents of E for other reasons. Of the orders which enter SI only
SAM, SIF, and SIA do not round the contents of A prior to storage in FO. The
fractional overflow, normalization and zero corrections are discussed below in
conjunction with the ST step.
In SI the RO status memory element is set to "1" for those orders which
round A prior to storage in FO, i.e., those orders for which \(j v Q v x) =1.
As discussed in section 3°lo7^ ro = 1 allows the roundoff, p, to assume a value
of "1" or "0" as determined by the bits in A, , , A, . , and Q. The RO memory ele
ment is set to "0" for the SAM, SIF, and SIA orders, i.e., the orders for which
\ " j0 p x = 1. Note that the x variable is unnecessary in these expressions. To
allow adequate time for the roundoff, p, to change the output of the carry gener
ator and Aadder, KgA is requested although the MsA mechanism is already set to
the KgA state. This request is always made even though RO is set to "0". As
pointed out in section 4.2, the MsAr response to this request is guaranteed to
be delayed enough to insure the cclogic signals (such as aov and na) are reli
able when the next control step  Sk in this case  becomes active.
When SI becomes active during the execution of an SSC, ASC, or STC
order, the TC memory element is set to "1". In this event the sSR selector
206
is set to QAsSR and V is set to "1" in preparation for an interchange and down
right shift into A. If store clear type orders are not being executed, TC is
set to "0" so OAsSR is the requested state of the sSR mechanism and V is set to
"0". This allows a to be placed in R and zero to be placed in S during Sk . A
zero must be placed in S when STN is the order. The MsS mechanism is always set
to OMsS to accommodate the terminal steps of store clear type orders.
The activity in the EAU during SI consists of placing the accumulator
exponent in EA and setting sD and C such that d = ea. The delay provided by
the KgA request gives the exponent decoder  EDM (D150^)  time to inspect
d and decide whether d < 6k.
During Sk f oc (rounded or unrounded) is placed in R while Q or zero is
placed in S depending on whether TC is set to "1" or "0". The Dadder output is
gated into ES and the Felements of the ED register are set to their new values
according to the output of the exponent decoder. In particular, the ES < 6k
Felement is set to "1" if d < 6k. An artificial delay is also used to pre
vent S5 from becoming active until the output of the R zero detector (DI505),
RZ, is reliable.
In describing the S5 step, we first assume STN is the order being exe
cuted. X is set to "l", so the contents of R are transferred to M. Since MsS
is requested and S contains zero, o = m = r = OC where OC represents the assimi
lated contents of A (rounded or unrounded) during SI.
Control passes to S6 where a is gated straight into A, and zero is
placed in Q. KgA is again requested simply to allow time for the Aadder out
put to reflect the new assimilated contents of A (new a). X is set to "0" to
prevent reentering S6 again when control passes through Sk and S5 the second
time .
When Sk becomes active the second time, (new Ot) = (old Qc) is placed
20^
in R while zero is again placed in S, The value of d has not changed, but gES
gates it into ES again. After a delay to allow RZ to "become reliable, S5 is ac
tivated for the second time.
Since X is set to "0", control may pass to S9 directly if fractional
overflow, normalization, or zero correction are unnecessary. Otherwise, control
passes to S7 and S8 where the necessary corrections are made,, We now investigate
the nature of these corrections,
N is set to "1" during Gl for the SSC, ASC, STR, XCH, STC, and STN or
ders. This means the fractional part of the operand being stored must lie in
the normalized range. For each of the above orders, the accumulator was normal
ized by the (r) sequence prior to the SI entry. However, the roundoff in SI may
cause the S5 contents of R to equal l/k or +1 both of which are outside the nor
malized range.
Of those orders which enter (sj through SI and round the contents of A
to R, J is set to "0" for STU, SSC, ASC, STR, XCH, STC, and STN. This means the
fractional operand being stored must not be overflowed. Note that if the frac
tion is guaranteed to be normalized when stored, it is also guaranteed to be
nonoverflowed. The converse of this is not always true. Of the above orders,
only STU does not guarantee that the fraction stored is normalized.
Under all circumstances, the Aadder output, CU, and the contents of R
agree during S5„ As discussed in section 3«1.9> no; = if a = \/h while net = 1
if a = +1. If 1 < a < 1, Cfov = 0, but if a = +1, aov = 1. Therefore, the con
dition Qtov = 1 must also be used to detect when OL is not normalized.
It is clear that if j = and (X = +1, the fractional overflow in R
must be corrected by an effective right shift of one base k position and the ex
ponent in ES (also contained by EA) increased by a unit to compensate for this
shift. In this case, j(aov) = 1 and n(na) , 0, so C is set to "l" and the sD
208
mechanism is left in the OsD state, yielding d = ea + 1 as required. The KgA
request provides sufficient delay for the output of exponent decoder  particu
larly the (d < 6k) signal to become reliable. The fraction in R is changed
to + l/k by the logic between the high end of R and FO. (See section 3.1.2.1U)
If n = 1 and CU = l/k f the fraction in R must be normalized by an
effective left shift of one base k position and the exponent in ES (also con
tained by EA) decreased by unit to compensate for this shift. Since n(na) = 1
and j(aov) =0, C is set to "l" and 2sD is requested to yield d = ea  1 as re
quired. KgA is again requested to allow time for the (d < 6k) output of the
exponent decoder to become reliable.
When n(na) = 1 or j(aov) = 1, it may also happen that
\[z v RZ ^ (es < 6k)] = 1. This does not affect the requests discussed above.
If \[z v RZ v (es < 6k)] = 1 and n(nCc) = j(aov) = 0, the exponent is left un
changed in S5 (i.e., C is set to "0" while the sD and MsA mechanisms are bypassed)
During S7, X.[z • RZ v (d < 6k)] is examined. If this expression has
a value of "1" (i.e., the condition is true), the number stored in FO during S9
is considered zero. Therefore, ES is cleared to 6k and R is cleared to zero.
The (ES < 6k) Felement in the ED register is cleared to "1" to denote the
change in ES. Note that Z is not set to "1", but it may already be in that
state. There are two other interesting observations. If es = 6k during S5
with \ = n(ndO = and j(aov) = 1, d = 63 during S7, so ES is not cleared to
6k. On the other hand if es = 63 during S5 with \ = j(aov) = and n(na) = 1,
d = 6k during S7, so ES is cleared to 6k. In any event, if
\[z •>/ RZ v (d < 6k)] = at the time S7 becomes active, the output of the D
adder (d = ea, d = ea + 1, or d = ea l) is gated into ES.
The S8 step is used only to check that (OUTFL)d = 1 before S9 becomes
active. This signal is "1" when AC has unloaded the previous contents of the
209
FO (OUT) and set OUTFL to "0" so S9 is free to load FO with bits from R and ES.
Returning to S5 momentarily, we note that the correction path is never
taken by the SAM order. SAM sets N to "0" and A to "1" during Gl. Since it
never rounds the contents of A during SI, Ctov = so j(aov) = 0. Consequently,
SAM simply uses S5 as a null step to check that ( OUTFL )d = 1 before activating
S9. Except for STN, the other orders which use SI also use S5 in the same way
if fractional overflow, normalization, or zero correction is unnecessary.
Before considering the action during S9, we return to the S2 and S3
entries.
SAL and SEX enter S2 directly from decode. SAL stores O.q q ... %
in FO through FO, , and es/, es . . . es in FO, through FO . SEX stores
0.q_ 1 q Q ... Qog in F0 through FO g and es , es , es , es , es , es , esg,
es . . . es in FO through FO .
In S2, the contents of Q are shifted right into R with "0" placed in
R and R n since V is set to "1". This is described in section 3.1.2.12. The
exponent of AQ appears at the output of the Dadder and is gated into ES. Con
trol then passes to S3 which is used as a null step to check that ( OUTFL )d = 1
prior to activating S9.
The SRM order enters S3 directly from decode. It is used primarily
to store the remainder immediately following division. The (jj) sequence leaves
the fractional part of the remainder in R and its exponent in ES, so SRM needs on
ly to check that ( OUTFL )d = 1 prior to activating S9.
During S9, RESgFO transfers the bit configurations in R through
Ri i and ES^ through ES or a modified version of this configuration into FO
through FO . For SEX, X is set to "l" so the logic discussed in section
3.1.2.14 is used to copy es into FO through FO,, . OUTFL and RO are set to
"0" even though the latter may already be in the "0" state. OV is set to "l"
210
if j(aov) = 1, i.e., if a is overflowed and either STF or SEQ are being executed.
Trouble may arise here because RO is set to "0" at the same time. Since SIF and
SIA never round the contents of A in SI, Cfov = for these orders even though
j = 1. For SRM, j(ccov) = because Ot is never overflowed at the start of Gl.
0V is also set to "l" if z RZ \(es © es ^) = ^* That is, if the accumulator is
nonzero, R is nonzero, and an arithmetic store order is executed (this excludes
SAM, SAL and SEX), the number stored is overflowed if es £ es f. This is clearly
the case if es = and es/ = 1 because its exponent is at least +6U. If es = 1
and es/ = 0, its exponent is at most 65, so es is not overflowed. 0V is bypassed
instead of being set to "l" because RZ = 1 since R was cleared to zero in either
ST or D19 if es < 6k in S9.
When S10 becomes active, control passes via a null step to Bl in case
XCH is being executed, i.e., in case n(tc)0,0p =1. If other nonstore clear
type orders are being executed, (tc)(n v/ Q v 9 ) =1, so v is set to "0". This
is necessary only for the SAL and SEX orders, but it is done for all orders in
this category. When d = 0, the paths so > A and so *■ A are closed while
the paths Q!, * R and a, , * R are opened  assuming in all cases the proper
settings. After V is set to "0", control passes to Kl. Even though RO is set
"0", OC may be overflowed at this point so the (k) sequence must be entered. If
STN is being executed and AQ, contained 1 during SI, AQ contains +1 during S10.
For SSC, ASC, and STC, TC is set to "l" during S10. During SI q.,^ ... %^
was placed in S S ... S, , with S and S set to the value of the roundoff,
p. This represents the roundoff correction for the least significant half of
the original contents of AQ,. Since V was set to "l" and OMsS was requested dur
ing SI, so = s = p and so = s_ = p appear at the inputs to A and A
following the S10 request for l/l+SRsAQ,. Thus, after gA is opened in S10, the
bit configuration, p,p,q_ l q. Q ... %2.>% 2 is P laced in A _! A o tnrou g h \?\k'
•211
If the roundoff, p, was a unit, the least significant half of the original con
tents of AQ (contents during Si) is givan a negative sign as required. Since
the exponent of the original contents of AQ is still in EA, S10 sets C to "0"
and requests 22sD to produce the exponent, d = ea  22, for the new accumulator
contents .
In Sll, this new exponent is placed in E while V and TC are set to
"0". Control then passes to S12.
During S12, Q is cleared to zero and Z is set to "l" if
d = ea  22 < 128. Otherwise, Z is bypassed. In any case, control passes to
(k) where the accumulator is checked for zero. Note that oc is never overflowed
following a store clear type order.
5.8 The Shift Sequence (F
Only the LRS and SRS orders enter the \F) sequence directly. The STF,
SIF, SEQ, and SIA orders enter (^F) via {J?) which is discussed in section 5.9.
In all cases, the number of base h places that AQ, must be shifted is
equal to the output of the D adder, d, at the time Fl first becomes active.
For LRS and SRS, d equals the exponent that is placed in EM during Gl. For STF,
SIF, SEQ, and SIA, d = ex  e, which is formed during P2, where e is the ori
ginal exponent of AQ and ex = 0, 22, em during Gl, or 6 respectively.
If d > 0, the shift direction is right. The shift direction is left
if d < 0. When shifting right, the sign bit of the assimilated accumulator is
inserted at the left end of A and S provided A is set to "0". Zeros are insert
ed at the left end of A and S if A is set to "l" (i.e., if the logical orders
LRS and SRS are being executed). When shifting left, bits are lost at the left
end of A and S, and 0V is set to "l" if STF, SIF, SEQ, or SIA is the order
■212
being performed. OV is bypassed in LRS and SRS orders since they are logical
in nature.
Assume the Fl control step has just been activated by an entry from
Gl or P3 as shown on D127^. In either case, KgA = 1. The shift loop exit
EcclesJordan, EXF, is set to "0" during Gl or P3, but the loop may not be used.
It is used if (z v \)(^5dUU)(d = 0)= 1. It is bypassed to FU if z\ ^ (d = 0) = 1
An exit to F5 via a null step occurs if (z v ^(l^cU^)  ]_ g These conditions
are mutually exclusive and yield "l" identically when joined. We consider them
separately in the order given.
Suppose (z v \)(U5dUU)(d = 0) = 1. First, this condition requires
that Z be set to "0" or that an LRS or SRS is the order if Z is set to "l".
Second, the shift must be in the range: U5 < d < hk. Third, d must not be 0.
The logic which generates the k^dkk signal is part of the exponent decoder
which is described in section 32.^ and shown on EDM (DI50U). If d = k^ } the
left shift moves the bits in Q, and Q, > to A and A , and places zeros in all
positions to the right of A . The AQ register could just as well have been
cleared to zero in this case, since Q, _ and Q, , are always cleared to zero
during Gl. The limit d = U5 is also used in decoding the fa #2 signal, so it
was convenient to use it for controlling the shift sequence. If d = kk, the
original assimilated sign bits, OC and a , are placed in Q, and Qr p . There
are no provisions for shortening these extreme shift operations for an SRS or
der. If d = 0, the entire shift loop is bypassed to Fk. To summarize, Fl re
quests the various link mechanisms associated with the shift loop operation
when (z v \) = 1 and U5 < d < 1 or 1 < d < hk.
The Fl, F2 loop operates very much like the A9, A10 loop. During
the first pass through Fl and F2, the shift paths in the MAU are established
as well as a count loop between the ES and EA registers in the EAU. if d < 2
■213
during the first pass through Fl, 2sD is requested in F2. If d = 1 or d = 1
during Fl, then OsD is requested in F2. If d > 2 during Fl, 2sD is requested
during F2. If SRS is being executed, DL is set to "0" so only gS and gA are
opened during Fl and F2. In this case, hits are either lost or zeros inserted
at the right end of S and A while the contents of R and Q remain unchanged.
As an example, assume d = 6 at the time Fl first becomes active.
The sEA mechanism is set to EsEA during decode and is unchanged at the time of
entry to (f) even via (V). Thus ESsEA = 1, so UAQsSR and OMsS are requested
while Tl is set to "l" just as in the first A9 step of the (A) loop. Opening
gS and gR (provided dj? = l) causes the assimilated output of the A adder
(KgA = l) and the contents of Q to be shifted left into SR. If A is set to
r
"0" and na = 1 (see section 3.1.9), OV is set to "1". That is, if a is nor
malized at this point, a left shift into S produces modulo 2 overflow as a
minimum, so OV is set to indicate this. At the same time, d = 6 is placed in
ES.
During the following F2 step, fl = 1 and es < 2 so ^SRsAQ, 2sD, KgA,
and ESsEA are requested, Opening gA and gQ (provided di = l) causes the assim
ilated output of the S adder (no stored carries in S) and the contents of R to
be shifted left into AQ. KgA is requested again in lieu of setting OMsA. When
gEA is opened and C set to "0", the new states of the sD and sEA mechanisms
cause d = h. If
"done" = (es == 2) " (es = l) v ( es = l) ^ (es = 2) ^ SZ(RZ ^ dj) = 1
EXF is set to "l" so that the next control step is F3 instead of Fl. In our ex
ample, "done" could only equal "l" if both S and R contained zero or if S con
tained zero and DL is set to "0". This possibility must be checked during
every cycle of the shift loop regardless of the shift direction. We assume
214
I
II J II
done" = on this pass through F2. If OV was set to 1 during Fl or if
\(ns)(es < 2) ■ 1, then OV is set to "1". Clearly, if es < 2 and the contents
of S are normalized, the left shift into A causes modulo 2 overflow at least.
Since A and S now contain assimilated representations, the na and ns signals
are used to detect imminent overflow during the remaining cycles through the
loop.
During the next pass through Fl, AQ is again shifted left into SR,
and d = k is placed in ES. 0, is set to "0" while the sSR and MsS mechanisms
1
are bypassed to obtain fast reply signals. OV is set to "l" if necessary.
In the following F2 step, SR is shifted left into AQ, and es = k is
placed in EA to produce d = 2. Since D, = and es = k, the sAQ, sD, MsA, and
sEA mechanisms are bypassed to obtain fast reply signals. OV is set to "l" if
necessary. Unless SZ(RZ ^ dj?) = 1, EXF is again set to "0" and control returns
to Fl.
During this third pass through Fl, the operations performed during
1
the preceding pass through Fl are repeated. OV is set to "l" if necessary.
During the following F2 step, SR is again shifted left into AQ by
opening gA and gQ while sAQ and MsA are bypassed. In the EAU, es = 2 is placed
in EA, causing d = 0. If d had been 5 originally, then es would equal 1 at
this point. The sAQ and sD mechanisms would then be set to SRsAQ and OsD so
that SR could be gated straight into AQ. Whether d = 6 or 5 originally,
"done" is "1" at this point, so EXF is set to "1" meaning that F3 is active next
in place of Fl. If es = 2 and \(ns) = 1, OV is set to "1" for the reason
given above. If es = 1 and \(ns) = 1, OV is bypassed since the output of SR
is gated straight into AQ, and overflow does not occur.
In the F3 step, DL is set to "1" to permit inspection of both A and Q
for zero in K2 if necessary. The a„gA gate insures that AQ is not overflowed
2.I5
modulo 2 when entering either the [Kj or {Sj sequences. Note that if a , £ a„
at the "beginning of the F3 step, OV was set to "l" during the last pass through
F2. When these operations are accomplished, control passes to Fk.
Fk is a null step that may be entered from Fl, F3, F8, or F9. Its
EcclesJordan is set to "l" only when F^ is entered from F3. In this case, the
null step acts as a delay to insure that the output of the roundoff logic is
reliable if RO is set to "1" during SI.
We now return to the initial entry at Fl and assume z\ v (d = 0) = 1.
In this case, the loop is bypassed and control passes to Fk immediately. This
occurs for the STF, SIF, SEQ, and SIA orders if Z is set to "l". There is no
provision for bypassing Fl, F2 if LRS or SRS is the order and the accumulator
is zero (i.e., Z is set to "l"). The shift loop is bypassed for all six orders
which use (f) if d = at the time Fl is initially activated.
If (z ^ \)(k^,dkk) = 1 when Fl is first entered from Gl or P3, control
passes to F5 via a null step. This null step was necessary in the original de
sign, but is not needed now. The purpose of this special bypass is to place a
field of all zeros or units in A or AQ directly instead of using k6 left shifts
or U5 right shifts.
If \(d > 0)(Sign A) = 1, an arithmetic right shift of more than kk
places is required, and the contents of AQ or A has a negative sign. Conse
quently, a field of units must be placed in AQ, or A depending on whether
&Z = 1 or dj} = 0. Therefore, F5 requests MMsS,CS and bypasses MsS. Since the
accumulator is not overflowed by a right shift, 0V is bypassed.
If \ ^ (d > 0)(Sign A) = 1, either a logical shift of more than kk
places is required, or else an arithmetic right shift of more than kk places
with a positive accumulator is required. In either case, a field of zeros must
he placed in AQ or A depending on whether &£ = 1 or dJJ = 0. OMsS is requested
216
while MMsS and CS are bypassed. AQ is not overflowed, so OV is bypassed. In
terms of reply circuitry, it would have been more economical to request KMsS
instead of OMsS. This would have avoided the need to bypass MsS, MMsS and CS
in the three options of F5 .
If \(d > 0) =1, an arithmetic left shift of more than U5 places is
required. The accumulator overflows so OV is set to "1". If AQ had been zero,
the FlFU bypass would have occurred and F5 would not be active. Preparatory
to placing a field of zeros in AQ or A, OMsS is requested while MMsS and CS are
bypassed. Here again, KMsS should have been used in place of OMsS.
During F6, the output of the Sadder is gated straight into A while
Q is left unchanged. Since S contains zero, o = t, i.e., a is the output of
the MsS selector.
In F7, the contents of A, which are assimilated and either all zeros
or all units, appear at the output of the A adder unaltered because KgA = 1.
Thus, gR transfers a into R. KMsS is requested to clear the MsS mechanism to
the OMsS state as explained in section h.2.
As shown on D1275, control passes to F8. If &£ = 0, the SI or Kl
EcclesJordan is set to "l" via Fk, although the Fk Eccles Jordan remains at
"0" as shown on D127^. If di = 1, the new contents of R, which agree with the
present contents of A, are gated straight into Q and control passes to F9.
F9 is a null step in which the EcclesJordan in SI or Kl is set to
"1" via Fk, although the Fk EcclesJordan remains at "0". This null step acts
as a delay to insure that the output of the roundoff logic is reliable if
R0 is set to "1" during SI.
5.9 The Store Preliminaries Sequence P)
The logic for this sequence appears on D1275. The (P) sequence is
>17
used by the STF, SIF, SEQ, and SIA orders. The purpose of this sequence is to
establish the number of base h places the accumulator must be shifted before its
exponent equals the one specified by STF (e = 0), SIF (e = 22), SEQ (e = em),
or SIA (e = 6).
At the start of each of these orders, Gl transfers the exponent of AQ
to EA from E and sets OsD and C„ Therefore, when PI becomes active, the expo
nent of AQ, appears at the output of the exponent adder, and the exponent of what
was in Fl (IN) during Gl is in EM„
During PI, d is placed in ES and E is loaded as follows:
STF » E SEQ em  E
SIF 22 » E SIA 6 > E
If the exponent decoder finds that d = when STF is the order being executed,
i.e., if 9 9 (d = 0) = 1, control passes to SI directly. Otherwise, the P2
EcclesJordan is set to "l".
In P2, the exponent of AQ, is transferred from ES to EM, and the contents
of E are placed in EA. By setting EMsD and C to "l", the new value of d may be
expressed as follows where em represents the present exponent of AQ and ea rep
resents the contents of EM during PI.
STF d =  em SEQ d = ea  em
SIF d = 22  em SIA d = 6  em
It is clear that d is the shift difference which is used by the (f) sequence
as explained in the preceding section.
During P3, the EXF EcclesJordan is set to "0" since control now
passes to Fl. Note that the actual request for EXF' appears on D127^.
■218
5.10 The Normalize Sequence Qy
The Qy sequence logic appears on D1282. It is the first sequence
after Gl for MPY, DIV, NDV, VID, STR, XCH, STC, STN, and DAV. (r) is used to
"normalize" the fraction, f, in AQ or A depending on whether DL is set to "1"
or "0". Except for MPY and DAV, the (r) sequence left shifts the fraction in
AQ or A until it is normalized (i.e., 1 < f < l/k, f = 0, or l/k < f < l).
In the case of MPY or DAV, the left shift stops when the fraction in AQ is normal
ized or when Q contains zero, whichever occurs first. For all cases except the
reentry from D4, DL is set to "l" so the contents of AQ are normalized. When (R
is entered from T)k, the fraction in A is normalized while the contents of Q are
left unchanged.
All entries to (RJ gate the EXR status memory element which controls
exit from the loop (Rl, R2). The positive logic for setting EXR to "l" (meaning
exit from the normalize loop) is given "below.
EXR = na >s z(d^) v (za)(dl) vn^Q^) ~ j(QZ)
It is important to note that if EXR is set to "l" during entry to Qy, then R3
instead of Rl becomes active  meaning the normalize loop is bypassed entirely.
This occurs if ot. is normalized (KgA = 1 so oc is the assimilated representation
of A), if Z is set to "l" initially, or if MPY or DAV is the order and Q con
tains zero, i.e., QZ = 1. Since ZA is always set to "0" during Gl, an immedi
ate bypass of (jy when entering from Dk is not possible. However, if A is found
to contain zero during any pass through R2, then ZA is set to "l" and exit oc
curs. Because the exponent of AQ or A is reduced by a unit for each base k left
shift of the fraction, underflow (i.e., d < 12$) may occur and set Z to "l"
during any pass through R2. In the case of MPY or DAV, Q may become zero during
any pass through R2, causing an exit from the normalize loop even though the
contents of AQ may not be normalized.
219
Assume that EXR is set to "0" during the initial entry to Rl. The
fraction to "be "normalized" is in AQ or A and its exponent is in E. KgA = 1,
so a is the assimilated representation of A. The assimilated contents of AQ or
A is shifted left into SR or S depending on whether DL is set to "l" or "0".
To allow the new contents of S to appear at the output of the Sadder as a, the
MsS mechanism is set to the zero state. The exponent in E, e, is placed in EA,
and the sD mechanism is set to 2sD. If a will appear normalized after a single
base h left shift, na  1. Otherwise, na = as discussed in section 3.1.9.
If the new contents of SR or S are normalized, na = 1 and the exponent should
!
only be decreased by a unit. Thus, na = 1 sets C to "l", leaving d = e  1.
If the new contents of SR or S are not normalized, na = and at least one more
base h left shift will be required, so the exponent should be decreased by two
units. Therefore, na = sets C to "0", leaving d = e  2.
During R2, the contents of SR or S (now in assimilated form) are gated
left or straight into AQ depending on whether C is set to "0" or "l" as explained
above. The output of the exponent adder, d=elord=e2is placed in E.
If d < 128, dz = 1 so Z is set to "l", indicating that the accumulator is now
considered zero. If S is found to contain zero, sZ = 1 so ZA is set to "l" pro
vided DL is set to "0". That is, if S contains zero during this first pass
through R2 and a single length normalization is being performed ( ( R) entered
from Dk) , the number being normalized is zero. Furthermore, if R is gated in
to Q, the contents of Q may now be zero in which case QZ = 1. EXR is set to
"0" or "1" during R2 depending on the output of the logic given above.
If exr = 0, R becomes active again, and the loop continues until EXR
is set to "l". If exr = 1, R3 is activated instead of Rl, and control passes
to SI, VI, Ml, or Dl depending on the order. For STR, XCH, STC, and STN, n J = 1
so si is activated. For DAV, j = 1, so VI is activated. For MPY, n 9.9^ = 1, so
Ml is activated. For DIV, NDV, and VID, n j(y v ) = 1, so Dl is activated.
220
5.11 The Difference Absolute Value Sequence (v)
The logic for this sequence is shown on the right side of D1280. It
is used only by the DAV order as indicated in Table I.
When VI is activated following the Qy sequence, the accumulator is
either normalized or at least Q contains zero. During the first pass through
V2, V3, and V^, the contents of A are rounded and placed in M, while the abso
lute value of the contents of M is placed in A with Q, cleared to zero. During
the second pass through V2, V3, and VU, this process is repeated, and 9 is set
to "0" so that apm is formed by the Qu sequence.
When VI is activated following (r) , OL represents the rounded value of
the contents of Q. The exponent of the accumulator is placed in EA while the sD
mechanism is set to EMsD and C is set to "0". These operations establish the in
itial state of the EAU prior to entering the (a) sequence.
During V2, OL is placed in R while zero is placed in S. MsS is request
ed if M contains a positive number; MsS is requested if M contains a negative
number. Thus a = m .
In V3, m is placed in A while Q is cleared to zero. R0 is set to
"0" since roundoff is complete. Since j = 1, 9 is set to "l" to obtain a "0"
9 v signal even though 9 is already in the "1" state. This avoids a bypass
request to 9 .
During VU, the contents of R (a„) are placed in M. J is set to "0"
so that when V3 becomes active the next time, 9 will be set to "0". EXA is
set to "0" as a preparatory step to entering the [A) sequence.
Since 0=1 following the first pass through Vh, control returns to
V2. At this point, a^ appears in M and m appears in A. During V2, m is
placed in R and zero is again placed in S, If a is positive, MsS is requested.
If a„ is negative, MsS is requested. Therefore, a = jaJ.
221
In V3, aJ is placed in A while Q is again cleared to zero. RO is
again set to "0" simply to obtain a zero reply. During this pass through V3,
j = 0, so is set to "0".
In VU, m is transferred to M. J and EXA are both set to "0" again
to obtain "0" replies. Because d. = at this point, control passes to Al. Note
that 0=0 and the other status memory element settings for DAV cause a sub
traction to occur during the (T) sequence. The exponents of jm and ap are in
EM and EA respectively. Since EMsD and C were requested during VI, d = ea  em  1
appears at the output of the Dadder when Al becomes active.
It is interesting to note that m ~ j au. ] = +1 is a possible result of
the (v) sequence. The logic at the most significant end of the A register handles
this case correctly during the (AJ sequence.
If m j4 D and ap =0 when Al becomes active, control passes direc
l6 to Bl as discussed in section 5.2. The (b) sequence performs a CSB in the
usual manner.
5.12 The Multiply Sequence (m)
The logic for this sequence is shown on D128l. It is used following
fly in the execution of an MPY order as shown in Table I.
At the time Ml becomes active, the unrounded multiplier is in AQ, and E.
The fraction in AQ is normalized or at least Q contains zero. The multiplicand
resides in M and EM. If the multiplier is zero, Z is set to "1". If the multi
plicand is zero, em = 6k.
Let the rounded multiplier, which may or may not be normalized, be
represented by a_ • k . Let the multiplicand be represented by m • k . The
exponent of the product is formed in the EAU as e + em while the 90 bit frac
tional product is formed in the MAU as a_ ' m. Thus p • k = (a~ • m) • k
■222
As explained in section 3.1.15, the U6 bits fractional multiplier (in
cluding two sign bits) is recoded two bits at a time so that 2m, m, Om, and m are
the required multipliers of the fractional multiplicand. The 90 bit fractional
product (including two sign bits) is obtained with 23 additions and 22 right
shifts. The first two additions and right shifts occur during M3 and Uh . The
next 20 occur during M5 and M6 which comprise the multiply loop. The final addi
tion without shift into AQ occurs during M7.
As in section 3.1.15, assume each two bits of the rounded multiplier
represents a base h multiplier digit (3. so that a. (X , a a ... a, a, becomes
1
P n , (3, ... P pp where P. =0, 1, 2, 3. The recoded base k digits B. are defined
as follows
B. = B. + \.  k\. _
1 1 1 ll
where \ = \ = and \. = or 1 for < i < 21.
P i
The shifted partial products, j— , held in AQ and SR at each step of
t
the multiplication are listed below in terms of P..
1
M3
AQ: ~ = 1/k I B
22
m
L 1 *
m
Mh
SR: ^ = l/k \— + P Q1 m
h U 21
^21 W"
L 1+ U 2 
m
M5(lst) AQ:
P 20 P 21 u P 22^
■ + — 7; + '
h
k
kh
m
M6(lst)
1 1 t 1
OD V k f P 19 P 20 P 21 P 22l
SR: — = + —  + — r + — 57 m
^ U k 2 h 5 it.
'223
M.5(2nd) AQ: j 2 
m
M6(2nd) SR: jp =
m
M6(lOth) SR!
P,
22
k
"Pi P 2
— + —
4 U'
22
22
m
MT
AQ:
P = P
23
P +
— + —
k K'
22
U
22
m
During Ml, control passes to M8 via a null step if (em = 6K) ^ z = 1„
This null step is not necessary in the present control design.
In M8, Z is set to "l", indicating a zero product,, OV is bypassed
simply to obtain a zero reply and thus set the Gl Eccles Jordan to "1".
If z(em •: 6k) = 1 during Ml, the contents of A are rounded by setting
RO to "1" and requesting KgA„ The assimilated, rounded multiplier appears as OL,
The (J. status memory element is set to "1" to permit the mode bits of the recoded
multiplier to be gated into Ri_ and Q, as indicated in section 3.1.15. In the
EAU the exponent of the product appears as d = em + ea = em + e = ep.
During M2, the two least significant bits of the rounded multiplier,
(X _0£i i , are recoded to determine the setting of the MsS mechanism. At the same
time, OL is placed in R and zero is placed in S The mode bit that is generated
as a consequence of recoding aft, is also placed in Rj l0 , This bit influences
22U
the recoding of the next base k multiplier digit which is presently held in R. ,
and R. _. Note that the recoded version of a, _ and a« > is not stored in R but is
simply reflected in the setting of the MsS mechanism. This is true for all steps
of the multiplication process. In the EAU, ep is placed in E and the ESOV and
ESZ Felements are set to "l" if necessary. The count of 21 is selected as an
input to EA but is not actually gated into EA until M3.
In M3, 2m, m, Om, or m is added to in S to form the first partial
product, p, , which is then shifted right into AQ. At the same time, r, , r, ,
and r. are recoded by the uMsA logic which sets the MsA mechanism accordingly.
The generated mode bit is placed in Q, . The RO memeory element is set to "0"
as a cleanup operation. In the EAU, 21 is transferred to EA and 2sD is select
ed so that d = 19. If esov = 1, 0V is set to "1" to indicate ep > 127. If
esz =1, Z is set to "l" to indicate ep < 128. Otherwise, 0V and Z are by
passed.
P l
During MU, 2m, m, 0m, or m is added to r— in AQ to form p which is
*
then shifted right into SR. At the same time, q, , % , and q, are recoded
by the uMsS logic which sets the MsS mechanism accordingly. Tne new mode bit
is placed in Rl p » In the EAU, 19 is placed in ES while the output of ES is se
lected as the input to EA.
During each of the ten passes through M5, the new partial product,
which appears as o and the most significant portion of R, is shifted right into
AQ. The next base k multiplier digit, r ] l  [ r ] l o) along with the associated mode
bit, r, , is recoded and used to set the MsA mechanism. The new mode bit is
*
placed in Q^ p . The count held in ES is gated into EA.
During each of the ten passes through M6, the new partial product,
which appears as a and the most significant portion of 'Q, is shifted right into
SR, The next base h multiplier digit, cu q_s , together with its mode bit, q« p ,
■225
X
is recoded and used to set the MsS mechanism. The new mode bit is placed in R^ D .
The count d = ea  2 is placed in ES.
The final pass through M6 merits special attention. The sign digit
of the rounded multiplier, a J3. , is held in Qk,Qkp at the start of this step.
The new mode bit in Q. ? may be 1 or "0". The recoded digit, (3 , is determined
as usual. If a mode bit is generated, it is thrown away, since d = 1 and u
is set to "0". Thus, a "0" is gated into Rj,p. Note that if the rounded multi
plier is negative (i.e., a_ 1 = a = 1), p = 3. If q^ =0, £ = 1 as required.
If q, = 1, P n = again as required. In either case, the next mode bit is always
"0".
It is worthwhile to observe why R< p must be set to "0" during the final
pass through M6. The two least significant bits of the product (actually the
last shifted partial product) are placed in Ri and R» during this pass. In M7
the outputs of the borrow subtractor d and d, are gated into Q> , and Q, as
the two least significant bits of the product. Clearly, they should be copies
of r> and r, . However, they will not be unless Ri p is set to "0" as discussed
in section 3.1.17.
In M7, the final multiple of the multiplicand is added to the last
shifted partial product in SR to obtain the product as a together with the first
hk bits of R. The product is transferred straight into AQ, and KgA is selected
to assimilate the stored carries in A. The assimilated fractional product, p,
appears as a. together with the first hk bits of Q at the entrance to K . Note
that 1 < p < 1 at this point.
5.13 The Division Sequence (D
The logic for (d) is shown on D1271, D1272, and D1273. It is used
in conjunction with (i) and ® to execute DIV, NDV, and VID. Note that Dl, D2,
226
or D5 is always activated by a request from R3. Furthermore, if the divisor is
not normalized or if NDV or VID is the order, the (RJ sequence is reentered
from DU.
The requests made by the (d) sequence in Dl, D2, D3, and T)k depend on
the divide order and the range of the divisor (dividend in the case of VID).
At the start of D6, a fractional divisor in the range 1 < d <  l/k or
l/k < d < 1 appears in M while the fractional dividend in AQ, lies in the range
1 < D <  l/k f D = 0, or 1 U < D < 1. The corresponding quotient exponent, eq,
appears at the output of the exponent adder as d = ea  em = eD  ed = eq, where
eD and ed represent the "normalized" (l/k < x < l) dividend and divisor expo
nents respectively.
To insure that the fractional quotient is less than or equal to unity
in magnitude, the dividend D is subnormalized in D6. The subnormalized dividend
i i i r
D lies in the range  l/k < D <  l/l6, D = 0, or l/l6 < D < l/k. The frac
i
tional quotient q = — must lie in the range 1 < q <  l/l6 or l/l6 < q < 1
i
where D = results in a premature exit to G;. The corresponding exponent cor
t
rection eq = eq + 1 is not made at this point but is taken into account during
the terminal steps of the 'D/ sequence.
For all three divide orders a modified binary nonrestoring division
algorithm is used to generate the fractional quotient. The recursive relation
ships are given in section ^.l.l6. The modification consists of allowing the
predicted quotient "bits" to assume the values 1, 0, 1. The term "binary"
still applies since the weighting associated with each "bit", y., is still 2
As discussed in sections 3.1.16 and 3.1.17, the "bits" y^ n , and
> J 2k+1
y ? , (0 < k < 22 or 23), are generated separately and then recoded as a base k
quotient digit, q 1 , which may assume any value between 3 and 3.
The y "bit" is determined by the pMsS logic shown on D1507. This
227
logic is fed by m and the most significant outputs of the Aadder. The setting
of the MsS mechanism is also governed by this logic. If y_, _ = 1, 2MsS is
2k+l '
selected, while y = or 1 cause OMsS or 2MsS to he selected.
2K+I
The y "hit" is determined by the pMsA logic which also appears on
D1507. This logic is fed by m and the most significant outputs of the Sadder,
It also determines the setting of the MsA mechanism. The "bits" y = 1, 0, and
1 correspond to settings of MsA, OMsA, and MsA.
1 1
In D6, the OMsS setting and gH correspond to y =0 for all d and D .
The value of y n and the corresponding setting of the MsA mechanism are determined
during the following straight transfer into AQ with D . The partial remainders
(shifted or unshifted) that appear at each step of the division process are given
below.
D7: AQ: R Q = D  Od
D9: SR: ^ = r(R Q  y Q d) = ^d'  y Q d)
D10(lst pass): AQ: R 2 = kR ±  2^= kV  d(Uy Q + 5y )
Dll(lst pass): SR: UR = 2%'  d(2 y Q + 2 3 y x + 2 2 y g )
D10(2nd pass): AQ: R^ = 2V  d(2*V + 2 3 y x + 2 2 y g + 2y 3 )
Dll(2nd pass): SR: 1+R^ = 2 6 D*  d(2 6 y Q + 2 3 y ± + 2^y 2 + 2 3 j^ + 2 2 y^)
/ \ kk ' / kk kl \
D10(22nd pass): AQ: R^ = 2 D  d(2 y Q + 2 ^ + . . . + 2y^)
Dll(22nd pass): SR: UR^ =2 d'  d(2 y Q + 2 5 y x + ... + 2 %i^)
228
The division process stops at this point if the fractional quottei .
i
q = y n y,yp ••• Y) ut appears "normalized" as discussed in section 3.1.10. Thus,
if nr = 1, the remainder associated with the unrounded quotient is
•kk ^ ,, ^1 „kk \ ,, J , ' „kkr
d(y Q + 2 y 1 + ... + 2 y^), so that D = dq + 2 R^ . If
nr + 0, the division process is allowed to proceed two more steps to obtain a
normalized quotient.
kf> ' h(~) Us
D10(23rd) AQ: R^ = 2 r D  d(2 y Q + 2 \ + . . . .+ 2y^)
Dll(23rd) SR: kR^ = 2 k8 B  d(2 U8 y Q + 2^ + ... + 2 2 y^)
The "bits" y = and y are discarded so that q = y.yp.y~yj ... y^c becomes
the "normalized" fractional quotient with 2 R, 7 = hB  m(2y + y + 2 Yvc)
kk '
as the remainder, or 4D  dq + 2 ^), 7 . Note that q or q denotes the fractional
quotient depending on whether it appears "normalized" after 23 or 2.k divide loop
cycles .
In either case one more quotient "bit" yj c (yj 7 ) is always determined
during the final pass through D10. This "bit" establishes the MsS setting during
Dll. Furthermore, y, (y< ) and a sign comparison of divisor and next partial
remainder (partial remainder beyond the final remainder) is used to round the
quotient positively, negatively, or not at all. The rules for roundoff are
given below. Refer to section 3.1.l6 for "the coding of V r (y, „),
4> 4(
y^(y^) ra_ 1 + a_ 1  cb Quotient RoundOff
kk
1 0.2
kk
1 1 1.2
kk
0.2
kk
1 ,0.2
kk
1 +1.2
kk
1 1 0.2
229
The quotient roundoff is determined while the shifted final remainder
kk , kk s
is in S. Therefore, the final remainder, R = 2 Ri < (or 2 ^wo ^ s corrected
for quotient roundoff before the latter is accomplished. That is, R = R + m
if the roundoff is negative, R = R  m if the roundoff is positive, and
R  R if the roundoff is zero. This occurs during DlU while q is in Q.
The actual roundoff of the quotient occurs in D17. The quotient in
Q is transferred to S and rounded appropriately during the straight gate into
Q in Dl8.
The quotient exponent, eq, must be corrected for subnormal! zat ion of
the dividend and possibly for the extra two steps in the divide loop (D10 and
Dll). This correction is made during D12 and D13, The corrected quotient ex
1
ponent, eq , is placed in E during Dl4 , The appropriate remainder exponent,
eR, is derived in D15, Dl6, and D17. It is placed in ES during D19 unless
eR < 6k in which case 6k is placed in ES.
We now proceed to describe each step of the (d) sequence in detail.
For all three divide orders, the contents of AQ are normalized before Dl, D2,
or D5 is activated. In discussing Dl through D5, it is convenient to consider
DIV and NDV first.
Assume that a DIV or NDV order is being executed and that the contents
of AQ during decode have just been normalized. On D1271 note that R3 must ac
tivate D2 or D5 rather than Dl since njx6,0 = except for a VID order. Note
ruther that D5 can only be activated when the number in M (i.e., the divisor)
is normalized, nm = 1, and the order is DIV, Under these conditions,
x(nm)e 6 = 1. The second possibility, xO 9 = 1, only applies for a VID order
following the second exit from MR) „ Assume that D2 becomes active either because
nm = or because the order is NDV,
In D2, a is placed in R and zero is placed in S. Since KgA = 1 during
■230
decode, a represents the assimilated contents of A. If DIV is the order, MsS
is requested so that the unnormalized divisor m = a appears at the output of the
Sadder. For NDV, MsS is requested so that m = a. In the EAU, the exponent
of the accumulator is placed in EA and reflected as d at the output of the Dadder
for either DIV or NDV.
During D3, m or m is placed in A and the gQ gate is "bypassed since
Q contains the least significant half of the dividend in the case of DIV or NDV
order. RO is set to "0" as a cleanup operation. Except for the VID order,
RO is already in the "0" state at the start of D3. Since X is always set to
"0" during Gl for DIV, NDV and VID, DL is set to "0" during this pass through D3.
In the EAU, d = eD (i.e., the exponent of the normalized dividend) is placed in
ES. Before normalization or negation the exponent of the divisor, em, is placed
in E.
In D^, the most significant half of the dividend is transferred from
R to M. X is set to "1" to indicate the first pass through D2, D3, and Dk,
In the EAU, eD is transferred from ES to EM. Since Dl is set to "0", D6 cannot
he activated. For DIV and NDV either Q or 6 is set to "0" so that
dl(z ^ 9 ^ 6 ) = 1. This is the condition for setting EXR to "0" or "1" via
gEXR and the input function discussed in section 5.10. EXR is set to "0" if the
fractional divisor (m or m) is not normalized. Since ZA is always set to "0"
during Gl, D5 cannot be activated because the A register contains a zero at this
point. Hence, for DIV and NDV, a premature exit to Gl via D5 with OV set to "l"
cannot occur during this pass through D2, D3, and D4. It can occur for VID if
Z is set to "1" as discussed later.
The signal which opens the gate to EXR also activates Rl. If EXR is
set to "1", R3 becomes active and control is transferred immediately to D2 in
the case of DIV or NDV. If EXR is set to "0", the normalization loop (Rl, R2)
231
is initiated. The principal difference is that dl = 0, so only the contents of
A are normalized. The other difference is that ZA is set to "1" if S contains
zero during the first pass through R2. The exponent of the unnormalized divisor
is decreased by a unit for each left shift of the fractional part in A. Since
em > 6k initially if the fractional divisor is nonzero, the divisor must become
normalized before dz = 1 (i.e., before the Dadder output d > 128). Thus Z is
always bypassed during R2 in this second pass through Qy . If ZA is not set to
"1" during the initial pass through R2, (r) continues to normalize single length
until the fraction is normalized (i.e., na = l).
When control returns to D2, as it must for a DIV or NDV order , the
normalized fractional divisor, d, is in A with its exponents, ed, in E, During
D2 the contents of A (i.e., d) is placed in R and zero is placed in S. MsS is
selected so that a  m which represents the most significant half of the normal
ized fractional dividend. The divisor exponent, ed, is transferred from E to EA
and reflected at the otuput of the Dadder.
During D3, a = m is placed in A, but gQ is again bypassed. The norm
alized fractional dividend is now in AQ,. R0 is again set to "0" and DL is set to
"1" since x = 1 during the second p?.uis through D2, D3, and Dk . In the EAU, ed is
placed in ES while eD is transferred from EM to E.
During DU, the normalized divisor is transferred from R to M while ed
is placed in EM. X is again set to "l". D5 is now activated.
If za = 1, meaning that the fractional divisor is zero, 0V is set
to "1" and control is transferred to Gl. The normalized dividend may be zero
eD
in which case Z is also set to "1". Otherwise, D * k appears in AQ and E.
The divisor, d • k , appears in M and EM. If d = 0, ed = 66 provided em = 6k
during Gl.
If za = 0, dl(za) = 1 and the quotient exponent, eq = eD  ed, is
■232
formed at the output of the Dadder. This exponent may or may not be the expo
nent of the final quotient. It will be if q = (D/d) lies in the normalized range,
In this case, the effect of subnormalization in D6 (i.e., the effect of shifting
D one base k position to the right) is exactly canceled by the extra pass through
D10 and Dll to achieve a normalized quotient. If q = (D/d) lies outside the nor
malized range (i.e., 1 < q < h) f eq = eq + 1 will be the exponent of the final
' q
quotient q = t* . In this case the subnormalization of D is not canceled by an
extra pass through D10 and Dll since q appears normalized in R after 23 cycles
of the divide loop. The addition of zero or a unit to eq = eD  ed occurs during
D13 based on the count in ES after exit from the divide loop (D10, Dll).
We return now to the case of a VID order. This order considers the con
tents of the accumulator as the divisor. Following Gl, control is transferred
to R . The fraction in AQ is normalized as usual with exit from ( R) occurring
as a consequence of nO! = 1 or z(dl) = 1. In contrast with DIV and NDV, R3 acti
vates Dl since njxS 9 = 1.
During Dl, KgA is selected and RO is set to "l" so that cc represents
the rounded and assimilated value of A. It is this quantity which is used as
the fractional divisor. Since x = during this entry from (jy, control passes
to D2, D3, and DU where the data handling is identical to that of a DIV order.
The opening of qQ during D3 to clear Q to zero is the one exception to this.
During DU, the gate to the EXR status memory element is opened and Rl
is activated if Z is set to "0", i.e., if (dl)(z) = 1. If z = 1, the quantity
in AQ at the start of the VID order was determined to be zero during Cr) so the
divisor is zero. Hence, z9 9 = 1 activates D5 which sets OV to "l" and exits
to Gl.
If z = 0, the R sequence is entered for the second time. At this
point, M and EM contain the normalized and rounded divisor while the quantity
233
in A and E represents the single length dividend as brought in from memory during
Gl. Note that the fraction in M was rounded following normalization and may be
+1 or  l/k. Either of these values may be used as the fractional divisor which
is why m is used as the divisor sign bit in the predictor logic as discussed
in section ^.l.l6.
During this pass through (R), the fractional dividend is normalized
single length even though Q contains zero. Exit occurs when no: = 1 or (za)(dl) = 1,
Control is transferred from R3 to D5 since X was set to "l" during the previous
pass through Dk and 9 = 9=1 for VID.
In D5, the quotient exponent, eq = eD  ed, is calculated as described
for the DIV and NDV orders. Again, it is important to note that eq = eq + 1
rather than eq may be the exponent of the fractional quotient which is actually
computed.
From this point on the discussion encompasses all three divide orders.
During D5, the fractional dividend, D, is in AQ with its exponent, eD,
in E and EA while the fractional divisor, d, is in M with its exponent, ed, in
EM. While eq is computed in the EAU, the setting of Z is examined. If z = 0,
D6 is activated. If Z = 1, the dividend is zero in the case of a DIV or NDV
order, so D8 is activated.
During D8, R is cleared to zero and 6k is placed in ES so that a
zero remainder is stored if an SRM order follows the divide order. 0V is also
bypassed in order to activate Gl. This is the second premature exit from (in .
If D6 is activated following D5, the fractional dividend, D, is sub
normalized by shifting it right one base k position into SR. OMsS is selected
t
so that the most significant half of D = T)/k appears at the output of the
Sadder. To agree with this selection, gH sets the H memory element in the
pMsS predictor (D1507) to "l". The effect of this is described in section 3. 1.17.
23 J +
In case VID is the order being executed, dl = at this point. Therefore, DL is
set to "1" to permit double length left shifts during the first 23 steps of the
division process. In the EAU, eq = eD  ed is placed in ES via gES which also
gates the output of the exponent decoder into the ED register (D150U). The
count for the divide loop is established by placing 22 in E.
As a part of D6, a decision is made to activate DT or D8 depending on
whether (esz)(za) = 1 or 0. If this expression has a value of "1", eq > 128
and ZA is set to "0". This means the quotient exponent is not underflowed and,
in the case of a VID order the dividend is not zero. The converse holds if
(esz) ^ za = 1. In this case Z is set to "1" to indicate a zero quotient and con
trol passes to D8.
In D8, R is cleared to zero and 6k is placed in ES indicating a zero
remainder. Following D8, control is transferred to Gl as usual.
If control passes from D6 to TfJ , the subnormalized dividend, D , is
transferred straight into AQ,. The pMsA predictor determines the setting of the
MsA mechanism in the manner described in section 3«1«1°« If y is 1 or 1, G2
is set to "0" or "1" and H is set to "0". In the EAU, 22 is transferred from
E to EA. The selection of 2sD causes 21 to appear at the output of the Dadder
since C was previously set to "1". Furthermore, 0V is set to "l" if esov = 1
(i.e., if eq > 127). Otherwise, 0V is bypassed.
At the start of D9, the most significant half of the unassimilated
first partial remainder appears as a. The pMsS predictor logic determines the
setting of the MsS selector mechanism while OL and Q are shifted left into SR.
The outputs of the G , H , G , and H memory elements (DI507) are
recoded by the quotient digit recoder logic (DI507) to form a base k quotient
digit which may lie anywhere in the range 1 < q^ < 1 during this step of the
division process.
•235
As described in section 3.1.17 and shown on D152^, 5 must be "1"
before pi and pi i can be gated into Ri and R, , via gR. Inspection of D1272
will reveal that & = 1 during D9. It should also be noted on LQR (D152U) that
*
(3i cannot be set into Ri p by gR unless 6=1. This condition is not true dur
ing D9 so a "0" is placed in R , This is done to prevent the borrowsubtractor
logic from decreasing the first partial remainder by a unit in the least signifi
cant position (i.e., the U2nd position) during the straight transfer into Q in D10.
If q = 1, p, = p , = pi, = 1 during D9, but a "0" is placed in R, while "1" is
placed in Ri and R^r. Since q represents the unmodified base k sign digit of
the quotient, the "l"s in R, and Ri, will eventually be interpreted as 1 even
though they both have positive weight at this point.
During D9 and the rest of the division process, the EAU is used as a
counter. The output of the Dadder during D9 is d = 21. This output is placed
in E via DgE. The exponent of the normalized divisor, ed, is held in EM while
the quotient exponent, eq = eD  ed, is held in ES. At this point eq has not
been corrected in accordance with the subnormalization that occurred during D6.
Following the completion of D9, control passes to the divide loop
which consists of D10 and Dll. Exit to D12 depends on the count in the EAU hav
ing reached 1 and on the appearance of a "normalized" quotient in R as discussed
in section 3. 1.10
During every pass through D10, the new partial remainder at the output
of the Sadder and in the most significant end of R is transferred straight into
AQ. The partially formed quotient which resides in the remaining bits of R is
transferred into the corresponding bits of Q. If Ri p = 1, the borrowsubtractor
logic reduces the quotient by a unit in the U2nd position as described in sec
tion 3.1.17. If ri = 1 and r, _ = ri 1 = 0, a borrow is made in anticipation of
a negative quotient digit in the future. The bit which is borrowed is held as
236
a stored carry in Q, p since the quotient digit inserted in Rr p , R,d> an d Rj,k is
in fact zero. R<~ is set to "1" when 7 = 1, i.e., when the true sign of the
previous partial remainder in AQ and the sign of the divisor disagree. This means
a negative quotient digit will eventually occur even though the pMsS and pMsA
logic predicted a zero.
During each pass through D10, the pMsA logic at the output of the
Sadder determines the new setting of the MsA mechanism as MsA, OMsA, or MsA
and sets G and H accordingly. Furthermore, the contents of G and H are copied
into G, and H so that the recoder can determine the next base h quotient digit.
Note that even though this digit may be zero, f3, _ may be "l" because 7=1. As
shown on CG (DIO99), SEC (D1527), and DPa (DI507), 7 is "1" if the true sign
of the partial remainder placed in AQ disagree with the sign of the divisor; i.e.,
a negative quotient digit will eventually arise in the infinite quotient. Since
the borrow subtractor can only effect the last two bits of the quotient, a borrow
must be made on the next step in anticipation of this negative quotient digit as
explained above.
During every pass through D10, A~ is set to "1" so that f3, can be
placed in R, via gR. On the first 22 passes through D10, DL is set to 1 since
rd
a partial remainder is double length during this period. If a 23 — pass occurs,
it is because the quotient did not appear normalized in R (i.e., nr = 0) after
the 22nd pass through Dll. On the 23^ — pass es = 1 (i.e., 1 is in E), so DL
is set to "0" . This prevents the sign bits of the quotient from being placed
rd
in S, and S. , during the 23 — pass through Dll. If these bits are zeros, they
could do no harm, but if they are units they could affect the quotient roundoff.
rd
By setting DL to "0" during the 23 — pass through D10, it is guaranteed that
zeros are placed in S, and S, , .
237
The count in E is placed in EA during D10. Since 2sD is selected and
C is set to "1", d = ea  1 appears at the output of the Dadder.
During the first 22 passes through Dll, the new partial remainder at
the output of the Aadder and in the most significant end of Q is shifted left
into SR. The quotient contained by the remaining bits of Q is likewise shifted
left into R. The bit in Qi _ is lost as explained in section 3.1.17. The new
base k quotient digit (B^ 2 , p^~, p^, ) is gated into R^ , R^ , and R^. The
count, d = ea  1, is gated into E„ The output of the exponent decoder is also
gated into ED as usual.
rd
On the 23 — pass through Dll, zeros are gated into S, and S, « regard
rd
less of the contents of Q, and Q since DL was set to "0" during the 23 — pass
through D10. The reason for this is given above.
During all passes through Dll the pMsS logic at the output of the
Aadder determines the setting of the MsS mechanism as 2MsS, OMsS or 2MsS. It
! I t I
sets G, and H accordingly. Note that changing the contents of the G and H
will not affect the outputs of the quotient digit recoder (i.e., (\p> Phi> anc ^
p, , ). Note also that the quotient "bit", Yiniyurj), placed in G, and H during
the 22 — (23 — ) pass through Dll is not used to form the fractional quotient
(y, is used if nr = after the 22 — pass through Dll). Instead, this "bit"
is used in conjunction with the sign of the resulting partial remainder (as
placed in A during D12) to determine the quotient roundoff.
After 22 passes through Dll, es = 1 but the fractional quotient in
R may or may not appear normalized. If nr = 1, control passes directly to D12.
rd
If nr = 0, the 23 — pass through D10 and Dll is executed. At the end of the
rd
23 — pass through Dll, the quotient in R must appear normalized, so nr = 1 and
es = 2. Control then passes to D12.
In D12, the partial remainder, beyond the one which is corrected for
238
quotient roundoff and retained as the remainder, is placed in A. The normalized
quotient in R is placed in Q. KgA is selected so that the true sign of the ex
cess partial remainder in A appears as OC . The unmodified quotient exponent,
eq = eD  ed, is placed in EA. Note that the MsA request does not occur so the
contents of G, and H are not transferred to G and H .
In D13, the output of the carryborrow logic is gated into CB as shown
on SEC (D1527). Since A~ is still set to "1", cb is logically equivalent to 7.
There is no provision for remembering 7, so the carry borrow logic and the CB
memory element are used instead. This use necessitates the KgA request in D12.
1
The CB output is used in conjunction with the quotient digit contained by G, and
H, to determine the quotient roundoff.
In order to place the unshifted remainder back in A, OMsS is request
ed and V is set to "1". As discussed in section 3.1.2.6 and shown on HAS (D1522),
o = l permits sa and so to be gated into A and A via gA while a is
placed in A . Since OMsS is selected, sa and sa represent the assimilated
value of s , s , and s .
The unmodified quotient exponent, eq = eD  ed, is in EA at the start
of D13. This exponent may or may not be the true exponent of the fractional quo
tient in Q at this point. The initial subnormalization of D requires that a
unit be added to eq. However, if an extra cycle of the divide loop is required
to achieve a normalized quotient, a unit must be subtracted from eq + 1 leaving
eq. Therefore, eq is the true exponent of the fractional quotient in Q if an
extra cycle of the divide loop is required. In this case, the count placed in
E during the final pass through Dll was 2. Hence, the ES = 2 Felement in
the ED register is set to "1". This sets C to "0" during D13. Since D13 re
quests OsD, the quotient exponent appears at the output of the Dadder. If an
extra cycle of the divide loop is not required, the ES = 2 Felement is set
239
to "0" during the final pass through Dll. Hence C is set to "1" during D13 and
1
eq = dq + 1 as required.
During DlU, the remainder is corrected in accordance with the quotient
roundoff which occurs in D17. The uncorrected remainder multiplied "by h appears
in S at the start of DlU. It is right shifted into A during Dlk m Note that
this depends on V being set to "1". Note also that the bits in S, and S, , are
lost. If an extra cycle of the divide loop was required (i.e., if
l/h < D/d < l), these bits are both zero. If an extra cycle was not required,
(i.e., if 1 < D/d C h) , these bits are the two least significant bits of D. If
either of these are nonzero, (&k )(qU ) + R • h will not equal D^ . ZV, is
set to "0" since the output of the carry borrow logic was used during D13.
kk
As discussed earlier in this section, the quotient roundoff is 1.2
/ n kb
it m_ © a = cb = 1 and 2y. (2y. ) = 2, the roundoff is +1.2 if
m , © a = cb = and 2y. c .(2y, ) = +2, and the roundoff is zero otherwise.
1 t
The last quotient "bit" predicted, y, or y^ 7 , is held in G, and H, but is not
1 t
inserted in the fractional quotient. If yi.q(y). 7 ) = ~lj gi = 1 and h = 0. If
11. 1 1
^5^7) = +1 > g l = h l = °* If y k^ y h^ = °> g l = ° or X and h l = 1 '
The fractional divisor is added to the remainder in A to compensate
for a negative quotient roundoff. It is subtracted from the remainder in A to
compensate for a positive quotient roundoff. Zero is added to the remainder
1 t
if the quotient roundoff is zero. Hence, MsA is requested if g h (cb) = 1;
MsA is requested if g h (cb) = 1; and By MsA (leaving KgA as the setting) is
requested if h, ^ (g , © cb) = 1.
The exponent of the fractional quotient in Q, eq, or eq is gated
into E during DlU. Note that C is still set to "0" if an extra cycle of the
divide loop was required but is set to "1" otherwise. Note also that the
1
ESOV Felement in the ED register is set to "1" if eq or eq > 127.
In D15, the fractional remainder corrected for quotient roundoff, R ,
2U0
appears as a and is shifted left into S. OV is set to "1" if esov  1 and is
bypassed otherwise. The divisor exponent is added to eq or eq by requesting
EMsD. Thus d = eq + c + ed appears at the output of the Dadder. Note that
d = eD  ed + c + ed = eD + c. Let the remainder exponent be denoted by eR.
If an extra cycle of the divide loop was required, eR = eD ■■  23 = cD  22.
If an extra cycle of the divide loop was not required, eR = eD  22 = eD  21.
Since C is set to "0" in the first case and to "1" in the second, it is clear
that eR = eD + c  22. This is accomplished during D17. In D15, eD + c appears
at the output of the Dadder.
During Dl6, kft. in S is shifted right into A and appears in assimilated
form at the output of the Aadder. Its magnitude is less that or equal to half
of the magnitude of the divisor. In the EAU eq + c is placed in ES. DL is set to
"0" to prevent the ! K; sequence from destroying the sign bits of the fractional
remainder in R in the event q or q = +1. This request is made during Dl6 simply
because it is convenient from the standpoint of physical layout. From a strictly
logical standpoint, it could have been made during D17, Dl8, D19, or D20.
During D17, the remainder, R , is placed in R while the quotient is
placed in S. If g h (cb) = 1, CS and By MM is requested to add a unit to q or
q in the hk — position. If g h (cb),= 1, CS and MMsS is requested to subtract
a unit from q or q in the Ui+—  position. Otherwise, zero is added to q or q
by requesting By CS and By MM. The rounded quotient thus appears at the output
of the Sadder. V is set to "0" since the right shift path from S to A is no
longer needed. In the EAU, C is set to "0" and 22sD is requested while eq + c
in ES is transferred to EA. Thus eR = eq + c  22 appears at the output of the
Dadder.
During Dl8, the rounded quotient is placed in A (it may be +l) while
Q is cleared to zero. Note that the quotient exponent, eq + c = eq or eq , is
2K1
held in E while eR is still appearing at the output of the Dadder.
In D19, the MsS selector mechanism is cleared to zero as usual follow
ing a possible MMsS or CS request. Zero is selected to SR. If the remainder in
R is zero, RZ = 1. If eR < 6k, then (d < 6k) = 1. In either case, R is cleared
to zero via a gR while 6k is placed in ES, Otherwise, the remainder is retained
in R and eR is gated into ES. Thus the remainder corrected for quotient round
off appears in R and ES at the end of any divide order. The [K) sequence cannot
affect it since DL is set to "0". The SRM order discussed in section 5.7 must
occur immediately after the divide order in the DC sequencing if the remainder is
to he retained.
A null step, D20, separates D19 from Kl since the gR reply is used in
both D19 and Kl.
2U2
JM PIT 1969